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Fix generate if, broke in earlier committ, bug492. Merge from Bennett.
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@ -369,7 +369,11 @@ private:
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// Extraction checks
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// Extraction checks
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bool warnSelect(AstSel* nodep) {
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bool warnSelect(AstSel* nodep) {
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AstNode* basefromp = AstArraySel::baseFromp(nodep);
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AstNode* basefromp = AstArraySel::baseFromp(nodep);
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if (m_doGenerate) V3Width::widthParamsEdit(nodep); // Never checked yet
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if (m_doGenerate) {
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// Never checked yet
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V3Width::widthParamsEdit(nodep);
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nodep->iterateChildren(*this); // May need "constifying"
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}
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if (AstNodeVarRef* varrefp = basefromp->castNodeVarRef()) {
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if (AstNodeVarRef* varrefp = basefromp->castNodeVarRef()) {
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AstVar* varp = varrefp->varp();
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AstVar* varp = varrefp->varp();
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if (!varp->dtypep()) varp->v3fatalSrc("Data type lost");
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if (!varp->dtypep()) varp->v3fatalSrc("Data type lost");
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19
test_regress/t/t_gen_cond_const.pl
Executable file
19
test_regress/t/t_gen_cond_const.pl
Executable file
@ -0,0 +1,19 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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compile (
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verilator_flags2 => ["--language 1364-2001"]
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);
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execute (
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check_finished=>1,
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);
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ok(1);
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1;
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71
test_regress/t/t_gen_cond_const.v
Normal file
71
test_regress/t/t_gen_cond_const.v
Normal file
@ -0,0 +1,71 @@
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// DESCRIPTION: Verilator: Verilog Test for generate IF constants
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//
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// The given generate loop should have a constant expression as argument. This
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// test checks it really does evaluate as constant.
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// This file ONLY is placed into the Public Domain, for any use, without
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// warranty, 2012 by Jeremy Bennett.
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`define MAX_SIZE 4
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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// Set the parameters, so that we use a size less than MAX_SIZE
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test_gen
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#(.SIZE (2),
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.MASK (4'b1111))
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i_test_gen (.clk (clk));
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// This is only a compilation test, but for good measure we do one clock
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// cycle.
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integer count;
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initial begin
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count = 0;
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end
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always @(posedge clk) begin
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if (count == 1) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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else begin
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count = count + 1;
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end
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end
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endmodule // t
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module test_gen
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#( parameter
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SIZE = `MAX_SIZE,
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MASK = `MAX_SIZE'b0)
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(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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// Generate blocks that rely on short-circuiting of the logic to avoid
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// errors.
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generate
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if ((SIZE < 8'h04) && MASK[0]) begin
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write ("Generate IF MASK[0] = %d\n", MASK[0]);
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`endif
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end
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end
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endgenerate
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endmodule
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