From 5a6f2b661d439c86e3ed41e33a28e25810264962 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Fri, 20 Sep 2024 20:34:35 -0400
Subject: [PATCH] Tests: Avoid multiple lint/compile runs in one test; hard to
 debug

---
 test_regress/t/t_std_identifier.py            | 16 +++++++++++++++
 ...td_identifier_bad.v => t_std_identifier.v} |  0
 test_regress/t/t_std_identifier_bad.out       |  2 +-
 test_regress/t/t_std_identifier_bad.py        |  3 +--
 test_regress/t/t_std_process_self.py          |  2 --
 test_regress/t/t_std_process_self_std.py      | 17 ++++++++++++++++
 test_regress/t/t_timing_fork_comb.py          |  2 --
 test_regress/t/t_timing_fork_comb_bad.py      | 19 ++++++++++++++++++
 test_regress/t/t_timing_intra_assign.py       |  4 ----
 .../t/t_timing_intra_assign_nolocalize.py     | 20 +++++++++++++++++++
 10 files changed, 74 insertions(+), 11 deletions(-)
 create mode 100755 test_regress/t/t_std_identifier.py
 rename test_regress/t/{t_std_identifier_bad.v => t_std_identifier.v} (100%)
 create mode 100755 test_regress/t/t_std_process_self_std.py
 create mode 100755 test_regress/t/t_timing_fork_comb_bad.py
 create mode 100755 test_regress/t/t_timing_intra_assign_nolocalize.py

diff --git a/test_regress/t/t_std_identifier.py b/test_regress/t/t_std_identifier.py
new file mode 100755
index 000000000..6938ef706
--- /dev/null
+++ b/test_regress/t/t_std_identifier.py
@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('linter')
+
+test.lint(verilator_flags2=["-DTEST_DECLARE_STD"])
+
+test.passes()
diff --git a/test_regress/t/t_std_identifier_bad.v b/test_regress/t/t_std_identifier.v
similarity index 100%
rename from test_regress/t/t_std_identifier_bad.v
rename to test_regress/t/t_std_identifier.v
diff --git a/test_regress/t/t_std_identifier_bad.out b/test_regress/t/t_std_identifier_bad.out
index 72bcf599b..c33ae7695 100644
--- a/test_regress/t/t_std_identifier_bad.out
+++ b/test_regress/t/t_std_identifier_bad.out
@@ -1,4 +1,4 @@
-%Error-PKGNODECL: t/t_std_identifier_bad.v:16:20: Package/class 'std' not found, and needs to be predeclared (IEEE 1800-2023 26.3)
+%Error-PKGNODECL: t/t_std_identifier.v:16:20: Package/class 'std' not found, and needs to be predeclared (IEEE 1800-2023 26.3)
    16 |     int baz = foo::std::bar;
       |                    ^~~
                   ... For error description see https://verilator.org/warn/PKGNODECL?v=latest
diff --git a/test_regress/t/t_std_identifier_bad.py b/test_regress/t/t_std_identifier_bad.py
index afd26c0f2..cdc19d5ba 100755
--- a/test_regress/t/t_std_identifier_bad.py
+++ b/test_regress/t/t_std_identifier_bad.py
@@ -10,9 +10,8 @@
 import vltest_bootstrap
 
 test.scenarios('linter')
+test.top_filename = "t/t_std_identifier.v"
 
 test.lint(fails=True, expect_filename=test.golden_filename)
 
-test.lint(verilator_flags2=["-DTEST_DECLARE_STD"])
-
 test.passes()
diff --git a/test_regress/t/t_std_process_self.py b/test_regress/t/t_std_process_self.py
index 3cb02e323..d8b6a325d 100755
--- a/test_regress/t/t_std_process_self.py
+++ b/test_regress/t/t_std_process_self.py
@@ -13,6 +13,4 @@ test.scenarios('simulator')
 
 test.lint(verilator_flags2=["--exe --main --timing"])
 
-test.lint(verilator_flags2=["--exe --main --timing --DUSE_STD_PREFIX"])
-
 test.passes()
diff --git a/test_regress/t/t_std_process_self_std.py b/test_regress/t/t_std_process_self_std.py
new file mode 100755
index 000000000..94cce2d22
--- /dev/null
+++ b/test_regress/t/t_std_process_self_std.py
@@ -0,0 +1,17 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_std_process_self.v"
+
+test.lint(verilator_flags2=["--exe --main --timing --DUSE_STD_PREFIX"])
+
+test.passes()
diff --git a/test_regress/t/t_timing_fork_comb.py b/test_regress/t/t_timing_fork_comb.py
index eb5fe00c7..421aad299 100755
--- a/test_regress/t/t_timing_fork_comb.py
+++ b/test_regress/t/t_timing_fork_comb.py
@@ -19,8 +19,6 @@ test.file_grep(
     r'%Warning-UNOPTFLAT: t/t_timing_fork_comb.v:\d+:\d+: Signal unoptimizable: Circular combinational logic:'
 )
 
-test.compile(verilator_flags2=["--exe --main --timing -Wno-UNOPTFLAT"])
-
 test.execute()
 
 test.passes()
diff --git a/test_regress/t/t_timing_fork_comb_bad.py b/test_regress/t/t_timing_fork_comb_bad.py
new file mode 100755
index 000000000..eceb2e20f
--- /dev/null
+++ b/test_regress/t/t_timing_fork_comb_bad.py
@@ -0,0 +1,19 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_timing_fork_comb.v"
+
+test.compile(verilator_flags2=["--exe --main --timing -Wno-UNOPTFLAT"])
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_timing_intra_assign.py b/test_regress/t/t_timing_intra_assign.py
index 2331869f2..1407fff26 100755
--- a/test_regress/t/t_timing_intra_assign.py
+++ b/test_regress/t/t_timing_intra_assign.py
@@ -15,8 +15,4 @@ test.compile(verilator_flags2=["--binary"])
 
 test.execute(expect_filename=test.golden_filename)
 
-test.compile(verilator_flags2=["--binary -fno-localize"])
-
-test.execute(expect_filename=test.golden_filename)
-
 test.passes()
diff --git a/test_regress/t/t_timing_intra_assign_nolocalize.py b/test_regress/t/t_timing_intra_assign_nolocalize.py
new file mode 100755
index 000000000..1f097a2b0
--- /dev/null
+++ b/test_regress/t/t_timing_intra_assign_nolocalize.py
@@ -0,0 +1,20 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_timing_intra_assign.v"
+test.golden_filename = "t/t_timing_intra_assign.out"
+
+test.compile(verilator_flags2=["--binary -fno-localize"])
+
+test.execute()
+
+test.passes()