diff --git a/src/V3Inst.cpp b/src/V3Inst.cpp
index 748a11158..7776a5de5 100644
--- a/src/V3Inst.cpp
+++ b/src/V3Inst.cpp
@@ -521,13 +521,14 @@ public:
         }
         const AstVarRef* const connectRefp = VN_CAST(pinp->exprp(), VarRef);
         const AstVarXRef* const connectXRefp = VN_CAST(pinp->exprp(), VarXRef);
-        const AstBasicDType* const pinBasicp
-            = VN_CAST(pinVarp->dtypep(), BasicDType);  // Maybe nullptr
-        const AstBasicDType* connBasicp = nullptr;
+        const AstNodeDType* const pinDTypep = pinVarp->dtypep()->skipRefp();
+        const AstBasicDType* const pinBasicp = VN_CAST(pinDTypep, BasicDType);
+        const AstNodeDType* const connDTypep
+            = connectRefp ? connectRefp->varp()->dtypep()->skipRefp() : nullptr;
+        const AstBasicDType* const connBasicp = VN_CAST(connDTypep, BasicDType);
         AstAssignW* assignp = nullptr;
-        if (connectRefp) connBasicp = VN_CAST(connectRefp->varp()->dtypep(), BasicDType);
         //
-        if (!alwaysCvt && connectRefp && connectRefp->varp()->dtypep()->sameTree(pinVarp->dtypep())
+        if (!alwaysCvt && connectRefp && connDTypep->sameTree(pinDTypep)
             && !connectRefp->varp()->isSc()) {  // Need the signal as a 'shell' to convert types
             // Done. Same data type
         } else if (!alwaysCvt && connectRefp && connectRefp->varp()->isIfaceRef()) {
diff --git a/test_regress/t/t_typedef_consistency_0.pl b/test_regress/t/t_typedef_consistency_0.pl
new file mode 100755
index 000000000..e64ab41be
--- /dev/null
+++ b/test_regress/t/t_typedef_consistency_0.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_typedef_consistency_0.v b/test_regress/t/t_typedef_consistency_0.v
new file mode 100644
index 000000000..14da498a0
--- /dev/null
+++ b/test_regress/t/t_typedef_consistency_0.v
@@ -0,0 +1,38 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2024 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+package pkg;
+   typedef logic l;
+endpackage
+
+module t(/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   wire logic  o_logic;
+   // Using 'pkg::l' instead of 'logic' should make no difference
+   wire pkg::l o_alias;
+
+   sub sub_logic(o_logic);
+   sub sub_alias(o_alias);
+
+   assign o_logic = clk;
+   assign o_alias = clk;
+
+   always @(posedge clk) begin
+     $display("o_logic: %b o_alias: %b", o_logic, o_alias);
+     // Whatever the answer is, it should be the same
+     if (o_logic !== o_alias) $stop;
+     $write("*-* All Finished *-*\n");
+     $finish;
+   end
+
+endmodule
+
+module sub(output wire  o);
+endmodule