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Fix array selects in sense lists
git-svn-id: file://localhost/svn/verilator/trunk/verilator@865 77ca24e4-aefa-0310-84f0-b9a241c72d87
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@ -100,7 +100,7 @@ private:
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virtual void visit(AstSenItem* nodep, AstNUser*) {
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// Remove bit selects, and bark if it's not a simple variable
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nodep->iterateChildren(*this);
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if (AstSel* selp = nodep->sensp()->castSel()) {
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while (AstNodeSel* selp = nodep->sensp()->castNodeSel()) {
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AstNode* fromp = selp->fromp()->unlinkFrBack();
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selp->replaceWith(fromp); selp->deleteTree(); selp=NULL;
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}
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@ -27,6 +27,13 @@ module t (/*AUTOARG*/
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end
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end
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reg [7:0] memory8_16_4;
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reg [7:0] memory8_16_5;
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always @ (memory8_16[4] or memory8_16[5]) begin
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memory8_16_4 = memory8_16[4];
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memory8_16_5 = memory8_16[5];
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end
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always @ (posedge clk) begin
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m_we <= 0;
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if (cyc!=0) begin
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@ -47,8 +54,8 @@ module t (/*AUTOARG*/
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m_data <= 16'h0bad;
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end
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if (cyc==5) begin
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if (memory8_16[4] != 8'h44) $stop;
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if (memory8_16[5] != 8'h55) $stop;
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if (memory8_16_4 != 8'h44) $stop;
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if (memory8_16_5 != 8'h55) $stop;
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if (memory8_16[6] != 8'hfe) $stop;
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if (memory8_16[7] != 8'h77) $stop;
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$write("*-* All Finished *-*\n");
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