From 57c7d77af3215fc2236b109d5aa2de15c40a4423 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 11 Mar 2018 16:33:38 -0400
Subject: [PATCH] Tests: Future reduction or test.

---
 test_regress/t/t_optm_redor.pl | 20 ++++++++
 test_regress/t/t_optm_redor.v  | 83 ++++++++++++++++++++++++++++++++++
 2 files changed, 103 insertions(+)
 create mode 100755 test_regress/t/t_optm_redor.pl
 create mode 100644 test_regress/t/t_optm_redor.v

diff --git a/test_regress/t/t_optm_redor.pl b/test_regress/t/t_optm_redor.pl
new file mode 100755
index 000000000..c39ed396f
--- /dev/null
+++ b/test_regress/t/t_optm_redor.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+file_grep_not ("$Self->{obj_dir}/$Self->{VM_PREFIX}.cpp", qr/rstn_r/);
+
+ok(1);
+1;
diff --git a/test_regress/t/t_optm_redor.v b/test_regress/t/t_optm_redor.v
new file mode 100644
index 000000000..b82e58b13
--- /dev/null
+++ b/test_regress/t/t_optm_redor.v
@@ -0,0 +1,83 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2017 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer      cyc=0;
+   reg [63:0]   crc;
+   reg [63:0]   sum;
+
+   // Take CRC data and apply to testblock inputs
+   wire [15:0]  in = crc[15:0];
+
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire                 out;                    // From test of Test.v
+   // End of automatics
+
+   Test test (/*AUTOINST*/
+              // Outputs
+              .out                      (out),
+              // Inputs
+              .in                       (in[15:0]));
+
+   // Aggregate outputs into a single result vector
+   wire [63:0] result = {63'h0, out};
+
+   // Test loop
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+      sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+      if (cyc==0) begin
+         // Setup
+         crc <= 64'h5aef0c8d_d70a4497;
+         sum <= '0;
+      end
+      else if (cyc<10) begin
+         sum <= '0;
+      end
+      else if (cyc<90) begin
+      end
+      else if (cyc==99) begin
+         $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+         if (crc !== 64'hc77bb9b3784ea091) $stop;
+         // What checksum will we end up with (above print should match)
+`define EXPECTED_SUM 64'h162c58b1635b8d6e
+         if (sum !== `EXPECTED_SUM) $stop;
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+
+endmodule
+
+module Test (/*AUTOARG*/
+   // Outputs
+   out,
+   // Inputs
+   in
+   );
+
+   input [15:0] in;
+   output reg   out;
+
+   // TODO this should flatten into a reduction OR
+   always_comb begin
+      out = 0;
+      for (int i=0; i<16; i=i+1) begin
+         if (in[i]) begin
+            out = 1;
+         end
+      end
+   end
+endmodule