From 5672b992035ecafcf6469e5b76f2cf91cec183cb Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 10 Dec 2006 22:48:26 +0000
Subject: [PATCH] Add t_extend_class example

git-svn-id: file://localhost/svn/verilator/trunk/verilator@836 77ca24e4-aefa-0310-84f0-b9a241c72d87
---
 test_regress/t/t_extend_class.pl  | 20 +++++++++++
 test_regress/t/t_extend_class.v   | 59 +++++++++++++++++++++++++++++++
 test_regress/t/t_extend_class_c.h | 17 +++++++++
 3 files changed, 96 insertions(+)
 create mode 100755 test_regress/t/t_extend_class.pl
 create mode 100644 test_regress/t/t_extend_class.v
 create mode 100644 test_regress/t/t_extend_class_c.h

diff --git a/test_regress/t/t_extend_class.pl b/test_regress/t/t_extend_class.pl
new file mode 100755
index 000000000..dd408f2c1
--- /dev/null
+++ b/test_regress/t/t_extend_class.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2006 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+if ($Last_Self->{v3}) {
+    compile (
+	     make_flags => 'CPPFLAGS_ADD=-I../t',
+	     );
+    execute (
+	     check_finished=>1,
+	     );
+}
+
+ok(1);
+1;
diff --git a/test_regress/t/t_extend_class.v b/test_regress/t/t_extend_class.v
new file mode 100644
index 000000000..6a22f6f55
--- /dev/null
+++ b/test_regress/t/t_extend_class.v
@@ -0,0 +1,59 @@
+// $Id$
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2003-2006 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+   reg [7:0] cyc; initial cyc=0;
+
+   reg [31:0] in;
+   wire [31:0] out;
+   t_extend_class_v sub (.in(in), .out(out));
+
+   always @ (posedge clk) begin
+      cyc <= cyc+8'd1;
+      if (cyc == 8'd1) begin
+	 in <= 32'h10;
+      end
+      if (cyc == 8'd2) begin
+	 if (out != 32'h11) $stop;
+      end
+      if (cyc == 8'd9) begin
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+endmodule
+
+module t_extend_class_v (/*AUTOARG*/
+   // Outputs
+   out,
+   // Inputs
+   in
+   );
+
+   input [31:0]  in;
+   output [31:0] out;
+
+   always @* begin
+      // When "in" changes, call my method
+      out = $c("m_myobjp->my_math(",in,")");
+   end
+
+ `systemc_header
+#include "t_extend_class_c.h"	// Header for contained object
+ `systemc_interface
+   t_extend_class_c* m_myobjp;	// Pointer to object we are embedding
+ `systemc_ctor
+   m_myobjp = new t_extend_class_c();	// Construct contained object
+ `systemc_dtor
+   delete m_myobjp;	// Destruct contained object
+ `verilog
+
+endmodule
diff --git a/test_regress/t/t_extend_class_c.h b/test_regress/t/t_extend_class_c.h
new file mode 100644
index 000000000..381006658
--- /dev/null
+++ b/test_regress/t/t_extend_class_c.h
@@ -0,0 +1,17 @@
+// $Id$ -*- C++ -*-
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2006-2006 by Wilson Snyder.
+
+class t_extend_class_c {
+public:
+    // CONSTRUCTORS
+    t_extend_class_c() {}
+    ~t_extend_class_c() {}
+    // METHODS
+    // This function will be called from a instance created in Verilog
+    inline uint32_t my_math(uint32_t in) {
+	return in+1;
+    }
+};