From 55c23360d9003a296930d0c1d2c93fc66ba5c54d Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Mon, 24 Sep 2012 18:28:19 -0400
Subject: [PATCH] Commentary

---
 bin/verilator | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/bin/verilator b/bin/verilator
index befeb60e4..98739f877 100755
--- a/bin/verilator
+++ b/bin/verilator
@@ -1058,6 +1058,7 @@ We'll compile this example into C++.
 	  Verilated::commandArgs(argc, argv);
           Vour* top = new Vour;
           while (!Verilated::gotFinish()) { top->eval(); }
+          delete top;
           exit(0);
       }
     EOF
@@ -1125,6 +1126,7 @@ This is an example similar to the above, but using SystemPerl.
           top = new Vour("top");   // SP_CELL (top, Vour);
           top->clk(clk);           // SP_PIN  (top, clk, clk);
           while (!Verilated::gotFinish()) { sc_start(1, SC_NS); }
+          delete top; 
           exit(0);
       }
     EOF
@@ -1423,6 +1425,7 @@ example:
 
 	    top->final();		// Done simulating
 	    //	  // (Though this example doesn't get here)
+	    delete top;
 	}
 
 Note signals are read and written as member variables of the lower module.