diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h
index 065869ce0..a212b8412 100644
--- a/src/V3AstNodes.h
+++ b/src/V3AstNodes.h
@@ -251,13 +251,6 @@ private:
 	m_trace=false;
     }
 public:
-    AstVar(FileLine* fl, AstVarType type, const string& name)
-	:AstNode(fl)
-	, m_name(name) {
-	init();
-	combineType(type);
-	width(msb()-lsb()+1,0);
-    }
     AstVar(FileLine* fl, AstVarType type, const string& name, AstRange* rangep, AstRange* arrayp=NULL)
 	:AstNode(fl)
 	, m_name(name) {
@@ -277,7 +270,7 @@ public:
 	if (examplep->arraysp()) {
 	    setOp2p(examplep->arraysp()->cloneTree(true));
 	}
-	width(msb()-lsb()+1,0);
+	width(examplep->width(), examplep->widthMin());
     }
     ASTNODE_NODE_FUNCS(Var, VAR)
     virtual void dump(ostream& str);
diff --git a/src/V3Clock.cpp b/src/V3Clock.cpp
index 6139433b6..f71ff2353 100644
--- a/src/V3Clock.cpp
+++ b/src/V3Clock.cpp
@@ -86,7 +86,7 @@ private:
 	if (varp->width()!=1) varp->v3error("Unsupported: Clock edge on non-single bit signal: "<<varp->prettyName());
 	string newvarname = ((string)"__Vclklast__"+vscp->scopep()->nameDotless()+"__"+varp->shortName());
 	AstVar* newvarp
-	    = new AstVar (vscp->fileline(), AstVarType::MODULETEMP, newvarname); // No range; 1 bit.
+	    = new AstVar (vscp->fileline(), AstVarType::MODULETEMP, newvarname, NULL, NULL); // No range; 1 bit.
 	newvarp->width(1,1);
 	m_modp->addStmtp(newvarp);
 	AstVarScope* newvscp = new AstVarScope(vscp->fileline(), m_scopep, newvarp);
diff --git a/src/V3Link.cpp b/src/V3Link.cpp
index 6bfd2c5f0..5c69721bf 100644
--- a/src/V3Link.cpp
+++ b/src/V3Link.cpp
@@ -156,7 +156,7 @@ private:
 	if (!forrefp->varp()) {
 	    if (!noWarn) forrefp->v3warn(IMPLICIT,"Signal definition not found, creating implicitly: "<<forrefp->prettyName());
 	    AstVar* newp = new AstVar (forrefp->fileline(), AstVarType::WIRE,
-				       forrefp->name());
+				       forrefp->name(), NULL, NULL);  // width 1
 	    newp->trace(m_modp->modTrace());
 	    m_modp->addStmtp(newp);
 	    // Link it to signal list