Fix core dump with initial variable delays

src/V3Width.cpp

@@ -2151,6 +2151,7 @@ private:
             userIterateAndNext(nodep->valuep(), WidthVP{nodep->dtypep(), PRELIM}.p());
             iterateCheckAssign(nodep, "Initial value", nodep->valuep(), FINAL, nodep->dtypep());
         }
+        userIterateAndNext(nodep->delayp(), WidthVP{nodep->dtypep(), PRELIM}.p());
         UINFO(4, "varWidthed " << nodep << endl);
         // if (debug()) nodep->dumpTree("-  InitOut: ");
         nodep->didWidth(true);

test_regress/t/t_delay_var.out

@@ -0,0 +1,5 @@
+%Error-ZERODLY: t/t_delay_var.v:20:7: Unsupported: #0 delays do not schedule process resumption in the Inactive region
+   20 |       #0 in = 1'b1;
+      |       ^
+                ... For error description see https://verilator.org/warn/ZERODLY?v=latest
+%Error: Exiting due to

test_regress/t/t_delay_var.pl

@@ -0,0 +1,30 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2023 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+if (!$Self->have_coroutines) {
+    skip("No coroutine support");
+}
+else {
+    compile(
+        verilator_flags2 => ["--exe --main --timing"],
+        make_main => 0,
+        fails => $Self->{vlt},
+        expect_filename => $Self->{golden_filename},
+        );
+
+    execute(
+        check_finished => 1,
+        ) if !$Self->{vlt};
+}
+
+ok(1);
+1;

test_regress/t/t_delay_var.v

@@ -0,0 +1,27 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+   parameter PDLY = 1.2;
+   real rdly = 1.3;
+   integer idly = 1;
+
+   reg in = 1'b0;
+
+   wire #1.1 d_const = in;
+   wire #idly d_int = in;
+   wire #rdly d_real = in;
+   wire #PDLY d_param = in;
+
+   initial begin
+      #0 in = 1'b1;
+      #2 in = 1'b0;
+      #100;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule

test_regress/t/t_net_delay.out

@@ -1,7 +1,15 @@
+%Warning-STMTDLY: t/t_net_delay.v:13:14: Ignoring delay on this statement due to --no-timing
+                                       : ... In instance t
+   13 |    wire[3:0] #4 val1 = cyc;
+      |              ^
+                  ... For warning description see https://verilator.org/warn/STMTDLY?v=latest
+                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.
+%Warning-STMTDLY: t/t_net_delay.v:14:14: Ignoring delay on this statement due to --no-timing
+                                       : ... In instance t
+   14 |    wire[3:0] #4 val2;
+      |              ^
 %Warning-ASSIGNDLY: t/t_net_delay.v:17:11: Ignoring timing control on this assignment/primitive due to --no-timing
                                          : ... In instance t
    17 |    assign #4 val2 = cyc;
       |           ^
-                    ... For warning description see https://verilator.org/warn/ASSIGNDLY?v=latest
-                    ... Use "/* verilator lint_off ASSIGNDLY */" and lint_on around source to disable this message.
 %Error: Exiting due to