Tests: bug795

test_regress/t/t_mem_slice_dtype_bad.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    fails=>1,
+    expect=>
+'%Error: t/t_mem_slice_dtype_bad.v:\d+: ADD unexpected in assignment to unpacked array
+.*%Error: Exiting due to.*',
+    );
+
+ok(1);
+1;

test_regress/t/t_mem_slice_dtype_bad.v

@@ -0,0 +1,40 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2014 by Alex Solomatnikov.
+
+typedef logic [$clog2(26+1)-1:0] way_cnt_t;
+
+module t(/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input logic clk;
+   int     cyc;
+
+   //bug795
+   way_cnt_t completed_cnt   [31:0][1:0];
+   way_cnt_t completed_cnt_dp        [1:0];
+
+   assign completed_cnt_dp = completed_cnt[id];
+
+   always_ff @(posedge clk) begin
+      completed_cnt[id] <= completed_cnt_dp + 1;
+   end
+
+   // bug796
+   logic [4:0] id;
+   logic [39:0] way_mask;
+   logic [39:0] addr[31:0][1:0];
+   always_ff @(posedge clk) begin
+      cyc <= cyc + 1;
+      id <= cyc[4:0];
+      if (cyc==1) begin
+         way_mask <= '0;
+         id <= 1;
+      end
+      else if (cyc==2) begin
+         assert((addr[id] & way_mask) == 0);
+      end
+  end
+endmodule