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Clock_enable is past experimental; bug50.

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Wilson Snyder 2009-01-20 07:24:57 -05:00
parent 8f88fa45f1
commit 4beaa45199
1 changed files with 5 additions and 5 deletions
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@ -1249,11 +1249,11 @@ The Verilog code returns to the last language mode specified with
=item /*verilator clock_enable*/
Experimental use only. Used after a signal declaration to indicate the
signal is used to gate a clock, and the user takes responsibility for
insuring there are no races related to it. (Typically by adding a latch,
and running static timing analysis.) This will cause the clock gate to be
ignored in the scheduling algorithm, improving performance.
Used after a signal declaration to indicate the signal is used to gate a
clock, and the user takes responsibility for insuring there are no races
related to it. (Typically by adding a latch, and running static timing
analysis.) This will cause the clock gate to be ignored in the scheduling
algorithm, improving performance.
=item /*verilator coverage_block_off*/