diff --git a/Changes b/Changes
index f47b8eac7..05f5ca324 100644
--- a/Changes
+++ b/Changes
@@ -74,6 +74,7 @@ Verilator 5.029 devel
 * Fix exponential concatenate performance (#5488). [Arkadiusz Kozdra, Antmicro Ltd.]
 * Fix V3Table trying to generate 'x' bits in the lookup table. (#5491). [Geza Lore]
 * Fix randomize with foreach constraints (#5492). [Arkadiusz Kozdra, Antmicro Ltd.]
+* Fix pattern initialization with typedef key (#5512). [Eugene Feinberg]
 
 
 Verilator 5.028 2024-08-21
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index cb3db1128..4f279e5b8 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -4408,9 +4408,10 @@ class WidthVisitor final : public VNVisitor {
                                 }
                                 memp = VN_AS(memp->nextp(), MemberDType);
                             }
-                        } else if (const AstNodeDType* nodedtypep
+                        } else if (AstNodeDType* nodedtypep
                                    = VN_CAST(patp->keyp(), NodeDType)) {
                             // data_type: default_value
+                            userIterate(nodedtypep, WidthVP{SELF, BOTH}.p());
                             const string dtype = nodedtypep->dtypep()->prettyDTypeName(true);
                             const auto pair = dtypemap.emplace(dtype, patp);
                             if (!pair.second) {
diff --git a/test_regress/t/t_array_pattern_enum.py b/test_regress/t/t_array_pattern_enum.py
new file mode 100755
index 000000000..d4f986441
--- /dev/null
+++ b/test_regress/t/t_array_pattern_enum.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_array_pattern_enum.v b/test_regress/t/t_array_pattern_enum.v
new file mode 100644
index 000000000..8581a1cee
--- /dev/null
+++ b/test_regress/t/t_array_pattern_enum.v
@@ -0,0 +1,32 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2024 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+package Pkg;
+   typedef enum {
+      RED=0,
+      GREEN=1,
+      BLUE=2
+   } color_t;
+
+   typedef struct {
+      color_t pixels[32];
+   } line_t;
+
+   typedef struct {
+      line_t line[32];
+   } screen_t;
+endpackage
+
+module t;
+   Pkg::screen_t screen;
+
+   initial begin
+      screen = '{ default: '0, Pkg::color_t: Pkg::RED};
+      $display("%p", screen);
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule