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Add error on soft constraints of randc
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@ -20,7 +20,7 @@ Verilator 5.031 devel
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* Add error on `wait` with missing `.triggered` (#4457).
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* Add error when improperly storing to parameter (#5147). [Gökçe Aydos]
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* Add coverage point hierarchy to coverage reports (#5575) (#5576). [Andrew Nolte]
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* Add error on `solve before` of `randc` variable.
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* Add error on `solve before` or soft constraints of `randc` variable.
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* Fix can't locate scope error in interface task delayed assignment (#5462) (#5568). [Zhou Shen]
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* Fix BLKANDNBLK for for VARXREFs (#5569). [Todd Strader]
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* Fix VPI error instead of fatal for vpi_get_value() on large signals (#5571). [Todd Strader]
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@ -2763,14 +2763,16 @@ public:
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class AstConstraintExpr final : public AstNodeStmt {
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// Constraint expression
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// @astgen op1 := exprp : AstNodeExpr
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bool m_isSoft = false; // Soft constraint expression
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bool m_isDisableSoft = false; // Disable soft constraint expression
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bool m_isSoft = false; // Soft constraint expression
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public:
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AstConstraintExpr(FileLine* fl, AstNodeExpr* exprp)
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: ASTGEN_SUPER_ConstraintExpr(fl) {
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this->exprp(exprp);
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}
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ASTGEN_MEMBERS_AstConstraintExpr;
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void dump(std::ostream& str) const override;
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void dumpJson(std::ostream& str) const override;
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bool isGateOptimizable() const override { return false; }
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bool isPredictOptimizable() const override { return false; }
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bool same(const AstNode* /*samep*/) const override { return true; }
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@ -376,6 +376,16 @@ void AstConstraint::dumpJson(std::ostream& str) const {
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dumpJsonBoolFunc(str, isStatic);
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dumpJsonGen(str);
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}
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void AstConstraintExpr::dump(std::ostream& str) const {
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this->AstNode::dump(str);
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if (isDisableSoft()) str << " [DISSOFT]";
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if (isSoft()) str << " [SOFT]";
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}
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void AstConstraintExpr::dumpJson(std::ostream& str) const {
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dumpJsonBoolFunc(str, isDisableSoft);
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dumpJsonBoolFunc(str, isSoft);
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dumpJsonGen(str);
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}
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AstConst* AstConst::parseParamLiteral(FileLine* fl, const string& literal) {
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bool success = false;
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if (literal[0] == '"') {
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@ -131,7 +131,9 @@ class RandomizeMarkVisitor final : public VNVisitor {
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BaseToDerivedMap m_baseToDerivedMap; // Mapping from base classes to classes that extend them
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AstClass* m_classp = nullptr; // Current class
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AstNode* m_constraintExprp = nullptr; // Current constraint expression
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AstConstraintBefore* m_constraintBeforep = nullptr; // Current before constraint
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AstConstraintExpr* m_constraintExprp = nullptr; // Current constraint expression
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AstNode* m_constraintExprGenp = nullptr; // Current constraint or constraint if expression
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AstNodeModule* m_modp; // Current module
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AstNodeStmt* m_stmtp = nullptr; // Current statement
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std::set<AstNodeVarRef*> m_staticRefs; // References to static variables under `with` clauses
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@ -402,50 +404,57 @@ class RandomizeMarkVisitor final : public VNVisitor {
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}
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}
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void visit(AstConstraintBefore* nodep) override {
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nodep->foreach([&](AstVarRef* const refp) {
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if (refp->varp() && refp->varp()->isRandC()) {
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nodep->v3error(
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"Randc variables not allowed in 'solve before' (IEEE 1800-2023 18.5.9)");
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}
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});
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VL_RESTORER(m_constraintBeforep);
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m_constraintBeforep = nodep;
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iterateChildrenConst(nodep);
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}
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void visit(AstConstraintExpr* nodep) override {
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VL_RESTORER(m_constraintExprp);
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m_constraintExprp = nodep;
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VL_RESTORER(m_constraintExprGenp);
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m_constraintExprGenp = nodep;
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iterateChildrenConst(nodep);
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}
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void visit(AstConstraintIf* nodep) override {
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{
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VL_RESTORER(m_constraintExprp);
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m_constraintExprp = nodep;
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VL_RESTORER(m_constraintExprGenp);
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m_constraintExprGenp = nodep;
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iterateConst(nodep->condp());
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}
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iterateAndNextConstNull(nodep->thensp());
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iterateAndNextConstNull(nodep->elsesp());
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}
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void visit(AstNodeVarRef* nodep) override {
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if (!m_constraintExprp) return;
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if (nodep->varp()->isRandC()) {
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if (m_constraintExprp && m_constraintExprp->isSoft()) {
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nodep->v3error(
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"Randc variables not allowed in 'constraint soft' (IEEE 1800-2023 18.5.13.1)");
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} else if (m_constraintBeforep) {
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nodep->v3error(
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"Randc variables not allowed in 'solve before' (IEEE 1800-2023 18.5.9)");
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}
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}
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if (!m_constraintExprGenp) return;
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if (nodep->varp()->lifetime().isStatic()) m_staticRefs.emplace(nodep);
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if (!nodep->varp()->rand().isRandomizable()) return;
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for (AstNode* backp = nodep; backp != m_constraintExprp && !backp->user1();
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for (AstNode* backp = nodep; backp != m_constraintExprGenp && !backp->user1();
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backp = backp->backp())
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backp->user1(true);
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}
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void visit(AstMemberSel* nodep) override {
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if (!m_constraintExprp) return;
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if (!m_constraintExprGenp) return;
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if (VN_IS(nodep->fromp(), LambdaArgRef)) {
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if (!nodep->varp()->rand().isRandomizable()) return;
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for (AstNode* backp = nodep; backp != m_constraintExprp && !backp->user1();
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for (AstNode* backp = nodep; backp != m_constraintExprGenp && !backp->user1();
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backp = backp->backp())
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backp->user1(true);
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}
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}
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void visit(AstArraySel* nodep) override {
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if (!m_constraintExprp) return;
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for (AstNode* backp = nodep; backp != m_constraintExprp && !backp->user1();
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if (!m_constraintExprGenp) return;
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for (AstNode* backp = nodep; backp != m_constraintExprGenp && !backp->user1();
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backp = backp->backp())
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backp->user1(true);
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iterateChildrenConst(nodep);
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@ -1,5 +1,5 @@
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%Error: t/t_randomize_before_randc_bad.v:11:29: Randc variables not allowed in 'solve before' (IEEE 1800-2023 18.5.9)
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%Error: t/t_randomize_before_randc_bad.v:11:45: Randc variables not allowed in 'solve before' (IEEE 1800-2023 18.5.9)
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: ... note: In instance 't'
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11 | constraint raint2_bad { solve b1 before b2; }
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| ^~~~~
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| ^~
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%Error: Exiting due to
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5
test_regress/t/t_randomize_soft_randc_bad.out
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5
test_regress/t/t_randomize_soft_randc_bad.out
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@ -0,0 +1,5 @@
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%Error: t/t_randomize_soft_randc_bad.v:10:28: Randc variables not allowed in 'constraint soft' (IEEE 1800-2023 18.5.13.1)
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: ... note: In instance 't'
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10 | constraint c_bad { soft rc > 4; }
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| ^~
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%Error: Exiting due to
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16
test_regress/t/t_randomize_soft_randc_bad.py
Executable file
16
test_regress/t/t_randomize_soft_randc_bad.py
Executable file
@ -0,0 +1,16 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('linter')
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test.lint(fails=test.vlt_all, expect_filename=test.golden_filename)
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test.passes()
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14
test_regress/t/t_randomize_soft_randc_bad.v
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14
test_regress/t/t_randomize_soft_randc_bad.v
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@ -0,0 +1,14 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Cls1;
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randc int rc;
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constraint c_bad { soft rc > 4; } // Bad, no soft on randc
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endclass
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module t (/*AUTOARG*/);
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endmodule
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