github/verilator
1
0
Fork 1
mirror of https://github.com/verilator/verilator.git synced 2025-07-31 07:56:10 +00:00
Code Issues Packages Projects Releases Wiki Activity

Test and fix extra end_keywords

Browse Source
This commit is contained in:
Wilson Snyder 2022-10-22 12:17:56 -04:00
parent 2df886b2b0
commit 495d52d30f
4 changed files with 41 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
src/verilog.l
View File

@ -1026,8 +1026,10 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
"`begin_keywords"[ \t]*\"1800-2012\" { FL_FWD; yy_push_state(S12); PARSEP->lexPushKeywords(YY_START); FL_BRK; }
"`begin_keywords"[ \t]*\"1800-2017\" { FL_FWD; yy_push_state(S17); PARSEP->lexPushKeywords(YY_START); FL_BRK; }
"`begin_keywords"[ \t]*\"1800[+]VAMS\" { FL_FWD; yy_push_state(SAX); PARSEP->lexPushKeywords(YY_START); FL_BRK; } /*Latest SV*/
"`end_keywords" { FL; yy_pop_state();
if (!PARSEP->lexPopKeywords()) yylval.fl->v3error("`end_keywords when not inside `begin_keywords block");
"`end_keywords" { FL;
if (!PARSEP->lexPopKeywords()) {
yylval.fl->v3error("`end_keywords when not inside `begin_keywords block");
} else { yy_pop_state(); }
FL_BRK; }
/* Verilator */
@ -1072,8 +1074,9 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
}
/* Catch all - absolutely last */
<*>.|\n { FL; yylval.fl->v3error("Missing verilog.l rule: Default rule invoked in state "
<< YY_START << " '" << yytext << "'");
<*>.|\n { FL; yylval.fl->v3error( // LCOV_EXCL_LINE
"Missing verilog.l rule: Default rule invoked in state "
<< YY_START << " '" << yytext << "'");
FL_BRK; }
%%
// Avoid code here as cl format misindents

4
test_regress/t/t_preproc_kwd_bad.out Normal file
View File

@ -0,0 +1,4 @@
%Error: t/t_preproc_kwd_bad.v:8:1: `end_keywords when not inside `begin_keywords block
8 | `end_keywords
| ^~~~~~~~~~~~~
%Error: Exiting due to

19
test_regress/t/t_preproc_kwd_bad.pl Executable file
View File

@ -0,0 +1,19 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(linter => 1);
lint(
fails => $Self->{vlt_all},
expect_filename => $Self->{golden_filename},
);
ok(1);
1;

11
test_regress/t/t_preproc_kwd_bad.v Normal file
View File

@ -0,0 +1,11 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`end_keywords
`end_keywords // BAD
module t;
endmodule