mirror of
https://github.com/verilator/verilator.git
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Support --bbox-unsup parsing of 'constraint', 'dist', 'solve'
This commit is contained in:
Wilson Snyder
parent
870ec27b73
commit
4862916f39
@ -374,6 +374,7 @@ void V3ParseImp::lexToken() {
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|| token == yGLOBAL__LEX //
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|| token == yLOCAL__LEX //
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|| token == yNEW__LEX //
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|| token == ySTATIC__LEX //
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|| token == yVIRTUAL__LEX //
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|| token == yWITH__LEX //
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// Never put yID_* here; below symbol table resolution would break
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@ -420,6 +421,12 @@ void V3ParseImp::lexToken() {
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} else {
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token = yNEW__ETC;
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}
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} else if (token == ySTATIC__LEX) {
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if (nexttok == yCONSTRAINT) {
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token = ySTATIC__CONSTRAINT;
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} else {
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token = ySTATIC__ETC;
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}
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} else if (token == yVIRTUAL__LEX) {
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if (nexttok == yCLASS) {
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token = yVIRTUAL__CLASS;
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@ -294,6 +294,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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"always" { FL; return yALWAYS; }
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"and" { FL; return yAND; }
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"assign" { FL; return yASSIGN; }
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"before" { FL; return yBEFORE; }
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"begin" { FL; return yBEGIN; }
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"buf" { FL; return yBUF; }
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"bufif0" { FL; return yBUFIF0; }
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@ -478,14 +479,14 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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"class" { FL; return yCLASS; }
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"clocking" { FL; return yCLOCKING; }
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"const" { FL; return yCONST__LEX; }
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"constraint" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
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"constraint" { FL; return yCONSTRAINT; }
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"context" { FL; return yCONTEXT; }
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"continue" { FL; return yCONTINUE; }
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"cover" { FL; return yCOVER; }
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"covergroup" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
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"coverpoint" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
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"cross" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
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"dist" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
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"dist" { FL; return yDIST; }
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"do" { FL; return yDO; }
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"endclass" { FL; return yENDCLASS; }
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"endclocking" { FL; return yENDCLOCKING; }
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@ -538,8 +539,8 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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"sequence" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
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"shortint" { FL; return ySHORTINT; }
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"shortreal" { FL; return ySHORTREAL; }
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"solve" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
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"static" { FL; return ySTATIC__ETC; }
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"solve" { FL; return ySOLVE; }
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"static" { FL; return ySTATIC__LEX; }
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"string" { FL; return ySTRING; }
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"struct" { FL; return ySTRUCT; }
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"super" { FL; return ySUPER; }
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@ -594,7 +595,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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"implements" { FL; return yIMPLEMENTS; }
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"interconnect" { ERROR_RSVD_WORD("SystemVerilog 2012"); }
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"nettype" { ERROR_RSVD_WORD("SystemVerilog 2012"); }
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"soft" { ERROR_RSVD_WORD("SystemVerilog 2012"); }
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"soft" { FL; return ySOFT; }
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}
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/* System Verilog 2017 */
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156
src/verilog.y
156
src/verilog.y
@ -421,7 +421,7 @@ class AstSenTree;
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%token<fl> yASSIGN "assign"
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%token<fl> yASSUME "assume"
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%token<fl> yAUTOMATIC "automatic"
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//UNSUP %token<fl> yBEFORE "before"
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%token<fl> yBEFORE "before"
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%token<fl> yBEGIN "begin"
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%token<fl> yBIND "bind"
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//UNSUP %token<fl> yBINS "bins"
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@ -441,7 +441,7 @@ class AstSenTree;
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//UNSUP %token<fl> yCLOCK "clock"
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%token<fl> yCLOCKING "clocking"
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%token<fl> yCMOS "cmos"
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//UNSUP %token<fl> yCONSTRAINT "constraint"
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%token<fl> yCONSTRAINT "constraint"
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%token<fl> yCONST__ETC "const"
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%token<fl> yCONST__LEX "const-in-lex"
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//UNSUP %token<fl> yCONST__LOCAL "const-then-local"
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@ -456,7 +456,7 @@ class AstSenTree;
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%token<fl> yDEFAULT "default"
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%token<fl> yDEFPARAM "defparam"
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%token<fl> yDISABLE "disable"
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//UNSUP %token<fl> yDIST "dist"
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%token<fl> yDIST "dist"
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%token<fl> yDO "do"
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%token<fl> yEDGE "edge"
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%token<fl> yELSE "else"
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@ -584,13 +584,13 @@ class AstSenTree;
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%token<fl> ySHORTINT "shortint"
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%token<fl> ySHORTREAL "shortreal"
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%token<fl> ySIGNED "signed"
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//UNSUP %token<fl> ySOFT "soft"
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//UNSUP %token<fl> ySOLVE "solve"
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%token<fl> ySOFT "soft"
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%token<fl> ySOLVE "solve"
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%token<fl> ySPECIFY "specify"
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%token<fl> ySPECPARAM "specparam"
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//UNSUP %token<fl> ySTATIC__CONSTRAINT "static-then-constraint"
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%token<fl> ySTATIC__CONSTRAINT "static-then-constraint"
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%token<fl> ySTATIC__ETC "static"
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//UNSUP %token<fl> ySTATIC__LEX "static-in-lex"
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%token<fl> ySTATIC__LEX "static-in-lex"
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%token<fl> ySTRING "string"
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//UNSUP %token<fl> ySTRONG "strong"
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%token<fl> ySTRUCT "struct"
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@ -910,8 +910,7 @@ class AstSenTree;
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%left '^' yP_XNOR
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%left '&' yP_NAND
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%left yP_EQUAL yP_NOTEQUAL yP_CASEEQUAL yP_CASENOTEQUAL yP_WILDEQUAL yP_WILDNOTEQUAL
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%left '>' '<' yP_GTE yP_LTE yP_LTE__IGNORE yINSIDE
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//UNSUP yDIST in above
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%left '>' '<' yP_GTE yP_LTE yP_LTE__IGNORE yINSIDE yDIST
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%left yP_SLEFT yP_SRIGHT yP_SSRIGHT
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%left '+' '-'
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%left '*' '/' '%'
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@ -3403,9 +3402,8 @@ function_subroutine_callNoMethod<nodep>: // IEEE: function_subroutine_call (as f
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// // IEEE: randomize_call
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// // We implement randomize as a normal funcRef, since randomize isn't a keyword
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// // Note yNULL is already part of expressions, so they come for free
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//UNSUP funcRef yWITH__CUR constraint_block { $$ = $1; BBUNSUP($2, "Unsupported: randomize() 'with'"); }
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//UNSUP remove the next line, temporary until have constraint_block (but enough for UVM parsing)
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| funcRef yWITH__CUR '{' '}' { $$ = $1; BBUNSUP($2, "Unsupported: randomize() 'with'"); }
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| funcRef yWITH__CUR constraint_block { $$ = $1; BBUNSUP($2, "Unsupported: randomize() 'with'"); }
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| funcRef yWITH__CUR '{' '}' { $$ = $1; BBUNSUP($2, "Unsupported: randomize() 'with'"); }
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;
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system_t_call<nodep>: // IEEE: system_tf_call (as task)
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@ -4094,7 +4092,7 @@ expr<nodep>: // IEEE: part of expression/constant_expression/primary
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//
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// // IEEE: expression_or_dist - here to avoid reduce problems
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// // "expr yDIST '{' dist_list '}'"
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//UNSUP ~l~expr yDIST '{' dist_list '}' { UNSUP }
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| ~l~expr yDIST '{' dist_list '}' { $$ = $1; BBUNSUP($2, "Unsupported: dist"); }
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;
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fexpr<nodep>: // For use as first part of statement (disambiguates <=)
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@ -5880,7 +5878,7 @@ class_itemList<nodep>:
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class_item<nodep>: // ==IEEE: class_item
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class_property { $$ = $1; }
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| class_method { $$ = $1; }
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//UNSUP class_constraint { $$ = $1; }
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| class_constraint { $$ = $1; }
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//
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| class_declaration { $$ = NULL; BBUNSUP($1, "Unsupported: class within class"); }
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| timeunits_declaration { $$ = $1; }
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@ -5943,86 +5941,86 @@ memberQualOne<nodep>: // IEEE: property_qualifier + method_qualifier
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//**********************************************************************
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// Constraints
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//UNSUPclass_constraint<nodep>: // ==IEEE: class_constraint
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//UNSUP // // IEEE: constraint_declaration
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//UNSUP constraintStaticE yCONSTRAINT idAny constraint_block { }
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//UNSUP // // IEEE: constraint_prototype + constraint_prototype_qualifier
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//UNSUP | constraintStaticE yCONSTRAINT idAny ';' { }
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//UNSUP | yEXTERN constraintStaticE yCONSTRAINT idAny ';' { }
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//UNSUP | yPURE constraintStaticE yCONSTRAINT idAny ';' { }
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//UNSUP ;
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class_constraint<nodep>: // ==IEEE: class_constraint
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// // IEEE: constraint_declaration
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constraintStaticE yCONSTRAINT idAny constraint_block { $$ = NULL; BBUNSUP($2, "Unsupported: constraint"); /*and audit all rules below for UNSUP*/ }
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// // IEEE: constraint_prototype + constraint_prototype_qualifier
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| constraintStaticE yCONSTRAINT idAny ';' { $$ = NULL; }
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| yEXTERN constraintStaticE yCONSTRAINT idAny ';' { $$ = NULL; BBUNSUP($1, "Unsupported: extern constraint"); }
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| yPURE constraintStaticE yCONSTRAINT idAny ';' { $$ = NULL; BBUNSUP($1, "Unsupported: pure constraint"); }
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;
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//UNSUPconstraint_block<nodep>: // ==IEEE: constraint_block
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//UNSUP '{' constraint_block_itemList '}' { $$ = $1; }
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//UNSUP ;
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constraint_block<nodep>: // ==IEEE: constraint_block
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'{' constraint_block_itemList '}' { $$ = $2; }
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;
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//UNSUPconstraint_block_itemList<nodep>: // IEEE: { constraint_block_item }
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//UNSUP constraint_block_item { $$ = $1; }
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//UNSUP | constraint_block_itemList constraint_block_item { $$ = AstNode::addNextNull($1, $2); }
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//UNSUP ;
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constraint_block_itemList<nodep>: // IEEE: { constraint_block_item }
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constraint_block_item { $$ = $1; }
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| constraint_block_itemList constraint_block_item { $$ = AstNode::addNextNull($1, $2); }
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;
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//UNSUPconstraint_block_item: // ==IEEE: constraint_block_item
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//UNSUP ySOLVE solve_before_list yBEFORE solve_before_list ';' { }
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//UNSUP | constraint_expression { $$ = $1; }
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//UNSUP ;
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constraint_block_item<nodep>: // ==IEEE: constraint_block_item
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constraint_expression { $$ = $1; }
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| ySOLVE solve_before_list yBEFORE solve_before_list ';' { $$ = NULL; BBUNSUP($2, "Unsupported: solve before"); }
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;
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//UNSUPsolve_before_list: // ==IEEE: solve_before_list
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//UNSUP constraint_primary { $$ = $1; }
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//UNSUP | solve_before_list ',' constraint_primary { }
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//UNSUP ;
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solve_before_list<nodep>: // ==IEEE: solve_before_list
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constraint_primary { $$ = $1; }
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| solve_before_list ',' constraint_primary { $$ = AstNode::addNextNull($1, $3); }
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;
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//UNSUPconstraint_primary: // ==IEEE: constraint_primary
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//UNSUP // // exprScope more general than: [ implicit_class_handle '.' | class_scope ] hierarchical_identifier select
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//UNSUP exprScope { $$ = $1; }
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//UNSUP ;
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constraint_primary<nodep>: // ==IEEE: constraint_primary
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// // exprScope more general than: [ implicit_class_handle '.' | class_scope ] hierarchical_identifier select
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exprScope { $$ = $1; }
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;
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//UNSUPconstraint_expressionList<nodep>: // ==IEEE: { constraint_expression }
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//UNSUP constraint_expression { $$ = $1; }
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//UNSUP | constraint_expressionList constraint_expression { $$ = AstNode::addNextNull($1, $2); }
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//UNSUP ;
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constraint_expressionList<nodep>: // ==IEEE: { constraint_expression }
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constraint_expression { $$ = $1; }
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| constraint_expressionList constraint_expression { $$ = AstNode::addNextNull($1, $2); }
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;
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//UNSUPconstraint_expression<nodep>: // ==IEEE: constraint_expression
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//UNSUP expr/*expression_or_dist*/ ';' { $$ = $1; }
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//UNSUP // // 1800-2012:
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//UNSUP | ySOFT expr/*expression_or_dist*/ ';' { }
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//UNSUP // // 1800-2012:
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//UNSUP // // IEEE: uniqueness_constraint ';'
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//UNSUP | yUNIQUE '{' open_range_list '}' { }
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//UNSUP // // IEEE: expr yP_MINUSGT constraint_set
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//UNSUP // // Conflicts with expr:"expr yP_MINUSGT expr"; rule moved there
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//UNSUP //
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//UNSUP | yIF '(' expr ')' constraint_set %prec prLOWER_THAN_ELSE { }
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//UNSUP | yIF '(' expr ')' constraint_set yELSE constraint_set { }
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//UNSUP // // IEEE says array_identifier here, but dotted accepted in VMM + 1800-2009
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//UNSUP | yFOREACH '(' idClassForeach/*array_id[loop_variables]*/ ')' constraint_set { }
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//UNSUP // // soft is 1800-2012
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//UNSUP | yDISABLE ySOFT expr/*constraint_primary*/ ';' { }
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//UNSUP ;
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constraint_expression<nodep>: // ==IEEE: constraint_expression
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expr/*expression_or_dist*/ ';' { $$ = $1; }
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// // 1800-2012:
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| ySOFT expr/*expression_or_dist*/ ';' { $$ = NULL; /*UNSUP*/ }
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// // 1800-2012:
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// // IEEE: uniqueness_constraint ';'
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| yUNIQUE '{' open_range_list '}' { $$ = NULL; /*UNSUP*/ }
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// // IEEE: expr yP_MINUSGT constraint_set
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// // Conflicts with expr:"expr yP_MINUSGT expr"; rule moved there
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//
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| yIF '(' expr ')' constraint_set %prec prLOWER_THAN_ELSE { $$ = NULL; /*UNSUP*/ }
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| yIF '(' expr ')' constraint_set yELSE constraint_set { $$ = NULL; /*UNSUP*/ }
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// // IEEE says array_identifier here, but dotted accepted in VMM + 1800-2009
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| yFOREACH '(' idClassForeach '[' loop_variables ']' ')' constraint_set { $$ = NULL; /*UNSUP*/ }
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// // soft is 1800-2012
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| yDISABLE ySOFT expr/*constraint_primary*/ ';' { $$ = NULL; /*UNSUP*/ }
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;
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//UNSUPconstraint_set<nodep>: // ==IEEE: constraint_set
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//UNSUP constraint_expression { $$ = $1; }
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//UNSUP | '{' constraint_expressionList '}' { $$ = $2; }
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//UNSUP ;
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constraint_set<nodep>: // ==IEEE: constraint_set
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constraint_expression { $$ = $1; }
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| '{' constraint_expressionList '}' { $$ = $2; }
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;
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//UNSUPdist_list<nodep>: // ==IEEE: dist_list
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//UNSUP dist_item { $$ = $1; }
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//UNSUP | dist_list ',' dist_item { $$ = AstNode::addNextNull($1, $3); }
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//UNSUP ;
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dist_list<nodep>: // ==IEEE: dist_list
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dist_item { $$ = $1; }
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| dist_list ',' dist_item { $$ = AstNode::addNextNull($1, $3); }
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;
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//UNSUPdist_item: // ==IEEE: dist_item + dist_weight
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//UNSUP value_range { $$ = $1; }
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//UNSUP | value_range yP_COLONEQ expr { }
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//UNSUP | value_range yP_COLONDIV expr { }
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//UNSUP ;
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dist_item<nodep>: // ==IEEE: dist_item + dist_weight
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value_range { $$ = $1; }
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| value_range yP_COLONEQ expr { $$ = $1; BBUNSUP($1, "Unsupported: dist :="); }
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| value_range yP_COLONDIV expr { $$ = $1; BBUNSUP($1, "Unsupported: dist :/"); }
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;
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//UNSUPextern_constraint_declaration: // ==IEEE: extern_constraint_declaration
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//UNSUP constraintStaticE yCONSTRAINT class_scope_id constraint_block { }
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//UNSUP ;
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//UNSUPconstraintStaticE<bool>: // IEEE: part of extern_constraint_declaration
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//UNSUP /* empty */ { $$ = false; }
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//UNSUP | ySTATIC__CONSTRAINT { $$ = true; }
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//UNSUP ;
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constraintStaticE<cbool>: // IEEE: part of extern_constraint_declaration
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/* empty */ { $$ = false; }
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| ySTATIC__CONSTRAINT { $$ = true; }
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;
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//**********************************************************************
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// Constants
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@ -1,4 +1,40 @@
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%Error: t/t_randomize.v:25:25: Unsupported: randomize() 'with'
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25 | v = p.randomize() with {};
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%Error: t/t_randomize.v:11:4: Unsupported: extern constraint
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11 | extern constraint ex;
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| ^~~~~~
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%Error: t/t_randomize.v:13:4: Unsupported: constraint
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13 | constraint a { header > 0 && header < 1000; }
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| ^~~~~~~~~~
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%Error: t/t_randomize.v:14:4: Unsupported: constraint
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14 | constraint b {
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| ^~~~~~~~~~
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%Error: t/t_randomize.v:19:4: Unsupported: constraint
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19 | constraint b {
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| ^~~~~~~~~~
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%Error: t/t_randomize.v:23:4: Unsupported: constraint
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23 | constraint c {
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| ^~~~~~~~~~
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%Error: t/t_randomize.v:29:29: Unsupported: solve before
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29 | constraint order { solve length before header; }
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| ^~~~~~
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%Error: t/t_randomize.v:29:4: Unsupported: constraint
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29 | constraint order { solve length before header; }
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| ^~~~~~~~~~
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%Error: t/t_randomize.v:32:16: Unsupported: dist :/
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32 | x dist { [100:102] :/ 1, 200 := 2, 300 := 5};
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| ^
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%Error: t/t_randomize.v:32:32: Unsupported: dist :=
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32 | x dist { [100:102] :/ 1, 200 := 2, 300 := 5};
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| ^~~
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%Error: t/t_randomize.v:32:42: Unsupported: dist :=
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32 | x dist { [100:102] :/ 1, 200 := 2, 300 := 5};
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| ^~~
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%Error: t/t_randomize.v:32:9: Unsupported: dist
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32 | x dist { [100:102] :/ 1, 200 := 2, 300 := 5};
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| ^~~~
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%Error: t/t_randomize.v:30:4: Unsupported: constraint
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30 | constraint dis {
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| ^~~~~~~~~~
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%Error: t/t_randomize.v:50:25: Unsupported: randomize() 'with'
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50 | v = p.randomize() with {};
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| ^~~~
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%Error: Exiting due to
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@ -7,6 +7,31 @@
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class Packet;
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rand int header;
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rand int length;
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extern constraint ex;
|
||||
|
||||
constraint a { header > 0 && header < 1000; }
|
||||
constraint b {
|
||||
if (64 > header) {
|
||||
header < (64'h1 << length);
|
||||
}
|
||||
}
|
||||
constraint b {
|
||||
header >= length - 10;
|
||||
header <= length;
|
||||
}
|
||||
constraint c {
|
||||
foreach (in_use[i]) {
|
||||
!(start_offset <= in_use[i].Xend_offsetX &&
|
||||
start_offset + len - 1 >= in_use[i].Xstart_offsetX);
|
||||
}
|
||||
}
|
||||
constraint order { solve length before header; }
|
||||
constraint dis {
|
||||
disable soft x;
|
||||
x dist { [100:102] :/ 1, 200 := 2, 300 := 5};
|
||||
}
|
||||
|
||||
endclass
|
||||
|
||||
module t (/*AUTOARG*/);
|
||||
|
||||
21
test_regress/t/t_randomize_bbox.pl
Executable file
21
test_regress/t/t_randomize_bbox.pl
Executable file
@ -0,0 +1,21 @@
|
||||
#!/usr/bin/env perl
|
||||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2019 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
scenarios(vlt => 1);
|
||||
|
||||
top_filename("t/t_randomize.v");
|
||||
|
||||
lint(
|
||||
verilator_flags => ["--bbox-unsup"],
|
||||
fails => 1,
|
||||
);
|
||||
|
||||
ok(1);
|
||||
1;
|
||||
Loading…
Reference in New Issue
Block a user