diff --git a/bin/verilator b/bin/verilator index 847ef3705..89e902a93 100755 --- a/bin/verilator +++ b/bin/verilator @@ -183,8 +183,8 @@ sub run { } if ($status & 127) { if (($status & 127) == 4 # SIGILL - || ($status & 127) == 8 # SIGFPA - || ($status & 127) == 11) { # SIGSEGV + || ($status & 127) == 8 # SIGFPA + || ($status & 127) == 11) { # SIGSEGV warn "%Error: Verilator internal fault, sorry. Consider trying --debug --gdbbt\n" if !$Debug; } elsif (($status & 127) == 6) { # SIGABRT warn "%Error: Verilator aborted. Consider trying --debug --gdbbt\n" if !$Debug; diff --git a/bin/verilator_includer b/bin/verilator_includer index c33eadcbe..3f2c58e29 100755 --- a/bin/verilator_includer +++ b/bin/verilator_includer @@ -13,8 +13,8 @@ use warnings; print "// DESCR"."IPTION: Generated by verilator_includer via makefile\n"; foreach my $param (@ARGV) { if ($param =~ /^-D([^=]+)=(.*)/) { - print "#define $1 $2\n" + print "#define $1 $2\n" } else { - print "#include \"$param\"\n" + print "#include \"$param\"\n" } } diff --git a/examples/hello_world_c/sim_main.cpp b/examples/hello_world_c/sim_main.cpp index 821553c33..08709e155 100644 --- a/examples/hello_world_c/sim_main.cpp +++ b/examples/hello_world_c/sim_main.cpp @@ -26,8 +26,8 @@ int main(int argc, char** argv, char** env) { // Simulate until $finish while (!Verilated::gotFinish()) { - // Evaluate model - top->eval(); + // Evaluate model + top->eval(); } // Final model cleanup diff --git a/examples/hello_world_sc/sc_main.cpp b/examples/hello_world_sc/sc_main.cpp index f31f54610..30ec5fdb7 100644 --- a/examples/hello_world_sc/sc_main.cpp +++ b/examples/hello_world_sc/sc_main.cpp @@ -37,9 +37,9 @@ int sc_main(int argc, char* argv[]) { // Simulate until $finish while (!Verilated::gotFinish()) { #if (SYSTEMC_VERSION>=20070314) - sc_start(1,SC_NS); + sc_start(1,SC_NS); #else - sc_start(1); + sc_start(1); #endif } diff --git a/examples/tracing_c/sim_main.cpp b/examples/tracing_c/sim_main.cpp index 004d7ade1..44dd601ea 100644 --- a/examples/tracing_c/sim_main.cpp +++ b/examples/tracing_c/sim_main.cpp @@ -63,33 +63,33 @@ int main(int argc, char** argv, char** env) { // Simulate until $finish while (!Verilated::gotFinish()) { - main_time++; // Time passes... + main_time++; // Time passes... - // Toggle clocks and such - top->fastclk = !top->fastclk; - if ((main_time % 10) == 3) { - top->clk = 1; - } - if ((main_time % 10) == 8) { - top->clk = 0; - } - if (main_time > 1 && main_time < 10) { - top->reset_l = !1; // Assert reset - } else { - top->reset_l = !0; // Deassert reset - } + // Toggle clocks and such + top->fastclk = !top->fastclk; + if ((main_time % 10) == 3) { + top->clk = 1; + } + if ((main_time % 10) == 8) { + top->clk = 0; + } + if (main_time > 1 && main_time < 10) { + top->reset_l = !1; // Assert reset + } else { + top->reset_l = !0; // Deassert reset + } - // Assign some other inputs - top->in_quad += 0x12; + // Assign some other inputs + top->in_quad += 0x12; - // Evaluate model - top->eval(); + // Evaluate model + top->eval(); - // Read outputs - VL_PRINTF ("[%" VL_PRI64 "d] clk=%x rstl=%x iquad=%" VL_PRI64 "x" - " -> oquad=%" VL_PRI64"x owide=%x_%08x_%08x\n", - main_time, top->clk, top->reset_l, top->in_quad, - top->out_quad, top->out_wide[2], top->out_wide[1], top->out_wide[0]); + // Read outputs + VL_PRINTF ("[%" VL_PRI64 "d] clk=%x rstl=%x iquad=%" VL_PRI64 "x" + " -> oquad=%" VL_PRI64"x owide=%x_%08x_%08x\n", + main_time, top->clk, top->reset_l, top->in_quad, + top->out_quad, top->out_wide[2], top->out_wide[1], top->out_wide[0]); } // Final model cleanup diff --git a/examples/tracing_c/sub.v b/examples/tracing_c/sub.v index 6f6fde7b6..e50d43d51 100644 --- a/examples/tracing_c/sub.v +++ b/examples/tracing_c/sub.v @@ -15,13 +15,13 @@ module sub reg [31:0] count_f; always_ff @ (posedge fastclk) begin if (!reset_l) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - count_f <= 32'h0; - // End of automatics + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + count_f <= 32'h0; + // End of automatics end else begin - count_f <= count_f + 1; + count_f <= count_f + 1; end end @@ -29,21 +29,21 @@ module sub reg [31:0] count_c; always_ff @ (posedge clk) begin if (!reset_l) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - count_c <= 32'h0; - // End of automatics + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + count_c <= 32'h0; + // End of automatics end else begin - count_c <= count_c + 1; - if (count_c >= 3) begin - $display("[%0t] fastclk is %0d times faster than clk\n", - $time, count_f/count_c); - // This write is a magic value the Makefile uses to make sure the - // test completes successfully. - $write("*-* All Finished *-*\n"); - $finish; - end + count_c <= count_c + 1; + if (count_c >= 3) begin + $display("[%0t] fastclk is %0d times faster than clk\n", + $time, count_f/count_c); + // This write is a magic value the Makefile uses to make sure the + // test completes successfully. + $write("*-* All Finished *-*\n"); + $finish; + end end end diff --git a/examples/tracing_c/top.v b/examples/tracing_c/top.v index e605270e2..65af1af13 100644 --- a/examples/tracing_c/top.v +++ b/examples/tracing_c/top.v @@ -10,29 +10,29 @@ module top ( // Declare some signals so we can see how I/O works - input clk, - input fastclk, - input reset_l, + input clk, + input fastclk, + input reset_l, output [1:0] out_small, output [39:0] out_quad, output [69:0] out_wide, - input [1:0] in_small, + input [1:0] in_small, input [39:0] in_quad, input [69:0] in_wide ); // Connect up the outputs, using some trivial logic - wire [1:0] out_small = ~reset_l ? '0 : (in_small + 2'b1); - wire [39:0] out_quad = ~reset_l ? '0 : (in_quad + 40'b1); - wire [69:0] out_wide = ~reset_l ? '0 : (in_wide + 70'b1); + wire [1:0] out_small = ~reset_l ? '0 : (in_small + 2'b1); + wire [39:0] out_quad = ~reset_l ? '0 : (in_quad + 40'b1); + wire [69:0] out_wide = ~reset_l ? '0 : (in_wide + 70'b1); // And an example sub module. The submodule will print stuff. sub sub (/*AUTOINST*/ - // Inputs - .clk (clk), - .fastclk (fastclk), - .reset_l (reset_l)); + // Inputs + .clk (clk), + .fastclk (fastclk), + .reset_l (reset_l)); // Print some stuff as an example initial begin diff --git a/examples/tracing_sc/sc_main.cpp b/examples/tracing_sc/sc_main.cpp index c78cc79d2..29ed072cb 100644 --- a/examples/tracing_sc/sc_main.cpp +++ b/examples/tracing_sc/sc_main.cpp @@ -99,21 +99,21 @@ int sc_main(int argc, char* argv[]) { // Simulate until $finish while (!Verilated::gotFinish()) { #if VM_TRACE - // Flush the wave files each cycle so we can immediately see the output - // Don't do this in "real" programs, do it in an abort() handler instead - if (tfp) tfp->flush(); - // Apply inputs - if (VL_TIME_Q() > 1 && VL_TIME_Q() < 10) { - reset_l = !1; // Assert reset - } else if (VL_TIME_Q() > 1) { - reset_l = !0; // Deassert reset - } + // Flush the wave files each cycle so we can immediately see the output + // Don't do this in "real" programs, do it in an abort() handler instead + if (tfp) tfp->flush(); + // Apply inputs + if (VL_TIME_Q() > 1 && VL_TIME_Q() < 10) { + reset_l = !1; // Assert reset + } else if (VL_TIME_Q() > 1) { + reset_l = !0; // Deassert reset + } #endif - // Simulate 1ns + // Simulate 1ns #if (SYSTEMC_VERSION>=20070314) - sc_start(1,SC_NS); + sc_start(1,SC_NS); #else - sc_start(1); + sc_start(1); #endif } diff --git a/examples/tracing_sc/sub.v b/examples/tracing_sc/sub.v index 6f6fde7b6..e50d43d51 100644 --- a/examples/tracing_sc/sub.v +++ b/examples/tracing_sc/sub.v @@ -15,13 +15,13 @@ module sub reg [31:0] count_f; always_ff @ (posedge fastclk) begin if (!reset_l) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - count_f <= 32'h0; - // End of automatics + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + count_f <= 32'h0; + // End of automatics end else begin - count_f <= count_f + 1; + count_f <= count_f + 1; end end @@ -29,21 +29,21 @@ module sub reg [31:0] count_c; always_ff @ (posedge clk) begin if (!reset_l) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - count_c <= 32'h0; - // End of automatics + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + count_c <= 32'h0; + // End of automatics end else begin - count_c <= count_c + 1; - if (count_c >= 3) begin - $display("[%0t] fastclk is %0d times faster than clk\n", - $time, count_f/count_c); - // This write is a magic value the Makefile uses to make sure the - // test completes successfully. - $write("*-* All Finished *-*\n"); - $finish; - end + count_c <= count_c + 1; + if (count_c >= 3) begin + $display("[%0t] fastclk is %0d times faster than clk\n", + $time, count_f/count_c); + // This write is a magic value the Makefile uses to make sure the + // test completes successfully. + $write("*-* All Finished *-*\n"); + $finish; + end end end diff --git a/examples/tracing_sc/top.v b/examples/tracing_sc/top.v index e605270e2..65af1af13 100644 --- a/examples/tracing_sc/top.v +++ b/examples/tracing_sc/top.v @@ -10,29 +10,29 @@ module top ( // Declare some signals so we can see how I/O works - input clk, - input fastclk, - input reset_l, + input clk, + input fastclk, + input reset_l, output [1:0] out_small, output [39:0] out_quad, output [69:0] out_wide, - input [1:0] in_small, + input [1:0] in_small, input [39:0] in_quad, input [69:0] in_wide ); // Connect up the outputs, using some trivial logic - wire [1:0] out_small = ~reset_l ? '0 : (in_small + 2'b1); - wire [39:0] out_quad = ~reset_l ? '0 : (in_quad + 40'b1); - wire [69:0] out_wide = ~reset_l ? '0 : (in_wide + 70'b1); + wire [1:0] out_small = ~reset_l ? '0 : (in_small + 2'b1); + wire [39:0] out_quad = ~reset_l ? '0 : (in_quad + 40'b1); + wire [69:0] out_wide = ~reset_l ? '0 : (in_wide + 70'b1); // And an example sub module. The submodule will print stuff. sub sub (/*AUTOINST*/ - // Inputs - .clk (clk), - .fastclk (fastclk), - .reset_l (reset_l)); + // Inputs + .clk (clk), + .fastclk (fastclk), + .reset_l (reset_l)); // Print some stuff as an example initial begin diff --git a/include/verilated_dpi.h b/include/verilated_dpi.h index ff9653bba..05eebe6ae 100644 --- a/include/verilated_dpi.h +++ b/include/verilated_dpi.h @@ -16,9 +16,9 @@ /// \file /// \brief Verilator: Common include for all Verilated C files that use DPI /// -/// This file is included automatically by Verilator at the top of -/// all C++ files it generates where DPI is used. It contains -/// DPI interface functions required by the Verilated code. +/// This file is included automatically by Verilator at the top of +/// all C++ files it generates where DPI is used. It contains +/// DPI interface functions required by the Verilated code. /// /// Code available from: http://www.veripool.org/verilator /// diff --git a/include/verilated_heavy.h b/include/verilated_heavy.h index cd5759ef4..faa523330 100644 --- a/include/verilated_heavy.h +++ b/include/verilated_heavy.h @@ -16,10 +16,10 @@ /// \file /// \brief Verilator: String include for all Verilated C files /// -/// This file is included automatically by Verilator at the top of -/// all C++ files it generates. It is used when strings or other -/// heavyweight types are required; these contents are not part of -/// verilated.h to save compile time when such types aren't used. +/// This file is included automatically by Verilator at the top of +/// all C++ files it generates. It is used when strings or other +/// heavyweight types are required; these contents are not part of +/// verilated.h to save compile time when such types aren't used. /// /// Code available from: http://www.veripool.org/verilator /// diff --git a/include/verilated_sc.h b/include/verilated_sc.h index ce8554889..3f42cb158 100644 --- a/include/verilated_sc.h +++ b/include/verilated_sc.h @@ -16,8 +16,8 @@ /// \file /// \brief Verilator: Common include for all Verilated SystemC files /// -/// This file is included automatically by Verilator at the top of -/// all SystemC files it generates. +/// This file is included automatically by Verilator at the top of +/// all SystemC files it generates. /// /// Code available from: http://www.veripool.org/verilator /// @@ -40,7 +40,7 @@ class VlScBvExposer : public sc_bv_base { public: static vluint32_t* sp_datap(const sc_bv_base& base) { - return static_cast(&base)->sp_datatp(); } + return static_cast(&base)->sp_datatp(); } vluint32_t* sp_datatp() const { return reinterpret_cast(m_data); } // Above reads this protected element in sc_bv_base: // sc_digit* m_data; // data array diff --git a/src/config_build.h.in b/src/config_build.h.in index 12dc0e8ae..ccfc1e553 100644 --- a/src/config_build.h.in +++ b/src/config_build.h.in @@ -26,7 +26,7 @@ // Autoconf substitutes this with the strings from AC_INIT. #define PACKAGE_STRING "" -#define DTVERSION PACKAGE_STRING +#define DTVERSION PACKAGE_STRING //********************************************************************** //**** Functions