From 43e1b27d16e9c7a9bc61631f22a1768e7c194ed4 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Thu, 14 Jan 2010 14:17:11 -0500 Subject: [PATCH] CDC: 'posedge a or posedge b or edge a' should optimize to 'edge a or posedge b' --- src/V3Const.cpp | 6 ++++-- src/Verilator.cpp | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/src/V3Const.cpp b/src/V3Const.cpp index 31754cce6..b37e9bbce 100644 --- a/src/V3Const.cpp +++ b/src/V3Const.cpp @@ -1167,8 +1167,6 @@ private: const AstSenItem* ritemp = rhsp->castSenItem(); if (litemp && ritemp) { // Looks visually better if we keep sorted by name - if (litemp->edgeType() < ritemp->edgeType()) return true; - if (litemp->edgeType() > ritemp->edgeType()) return false; if (!litemp->varrefp() && ritemp->varrefp()) return true; if ( litemp->varrefp() && !ritemp->varrefp()) return false; if (litemp->varrefp() && ritemp->varrefp()) { @@ -1178,6 +1176,10 @@ private: if (litemp->varrefp()->varScopep() < ritemp->varrefp()->varScopep()) return true; if (litemp->varrefp()->varScopep() > ritemp->varrefp()->varScopep()) return false; } + // Sort by edge, AFTER variable, as we want multiple edges for same var adjacent + // note the SenTree optimizer requires this order (more general firsst, less general last) + if (litemp->edgeType() < ritemp->edgeType()) return true; + if (litemp->edgeType() > ritemp->edgeType()) return false; } return false; } diff --git a/src/Verilator.cpp b/src/Verilator.cpp index 8dab53bb2..587c0a836 100644 --- a/src/Verilator.cpp +++ b/src/Verilator.cpp @@ -295,7 +295,7 @@ void process () { // Make large low-fanin logic blocks into lookup tables // This should probably be done much later, once we have common logic elimination. - if (v3Global.opt.oTable()) { + if (!v3Global.opt.lintOnly() && v3Global.opt.oTable()) { V3Table::tableAll(v3Global.rootp()); v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("table.tree")); }