github/verilator
1
0
Fork 1
mirror of https://github.com/verilator/verilator.git synced 2025-01-01 12:17:35 +00:00
Code Issues Packages Projects Releases Wiki Activity

Support multiple-output buf/not gate primitives

Browse Source
This commit is contained in:
Wilson Snyder 2023-01-28 23:20:48 -05:00
parent a19dddf05e
commit 4208db7811
3 changed files with 37 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
src/verilog.y
View File

@ -5117,10 +5117,28 @@ gateRangeE<nodep>:
;
gateBuf<nodep>:
gateFront variable_lvalue ',' gatePinExpr ')'
{ $$ = new AstAssignW{$<fl>1, $2, $4}; DEL($1); }
// UNSUP // IEEE: Multiple output variable_lvalues
// UNSUP // Causes conflict - need to take in variable_lvalue or a gatePinExpr
gateFront variable_lvalue ',' exprList ')'
{ AstNodeExpr* inp = $4;
while (inp->nextp()) inp = VN_AS(inp->nextp(), NodeExpr);
$$ = new AstAssignW{$<fl>1, $2, GRAMMARP->createGatePin(inp->cloneTree(false))};
for (AstNodeExpr* outp = $4; outp->nextp(); outp = VN_CAST(outp->nextp(), NodeExpr)) {
$$->addNext(new AstAssignW{$<fl>1, outp->cloneTree(false),
GRAMMARP->createGatePin(inp->cloneTree(false))});
}
DEL($1); DEL($4); }
;
gateNot<nodep>:
gateFront variable_lvalue ',' exprList ')'
{ AstNodeExpr* inp = $4;
while (inp->nextp()) inp = VN_AS(inp->nextp(), NodeExpr);
$$ = new AstAssignW{$<fl>1, $2, new AstNot{$<fl>1,
GRAMMARP->createGatePin(inp->cloneTree(false))}};
for (AstNodeExpr* outp = $4; outp->nextp(); outp = VN_CAST(outp->nextp(), NodeExpr)) {
$$->addNext(new AstAssignW{$<fl>1, outp->cloneTree(false),
new AstNot{$<fl>1,
GRAMMARP->createGatePin(inp->cloneTree(false))}});
}
DEL($1); DEL($4); }
;
gateBufif0<nodep>:
gateFront variable_lvalue ',' gatePinExpr ',' gatePinExpr ')'
@ -5130,12 +5148,6 @@ gateBufif1<nodep>:
gateFront variable_lvalue ',' gatePinExpr ',' gatePinExpr ')'
{ $$ = new AstAssignW{$<fl>1, $2, new AstBufIf1{$<fl>1, $6, $4}}; DEL($1); }
;
gateNot<nodep>:
gateFront variable_lvalue ',' gatePinExpr ')'
{ $$ = new AstAssignW{$<fl>1, $2, new AstNot{$<fl>1, $4}}; DEL($1); }
// UNSUP // IEEE: Multiple output variable_lvalues
// UNSUP // Causes conflict - need to take in variable_lvalue or a gatePinExpr
;
gateNotif0<nodep>:
gateFront variable_lvalue ',' gatePinExpr ',' gatePinExpr ')'
{ $$ = new AstAssignW{$<fl>1, $2, new AstBufIf1{$<fl>1, new AstNot{$<fl>1, $6},

16
test_regress/t/t_gate_basic.v
View File

@ -15,9 +15,10 @@ module t (/*AUTOARG*/
reg [31:0] a;
reg [31:0] b;
wire [2:0] bf; buf BF0 (bf[0], a[0]),
BF1 (bf[1], a[1]),
BF2 (bf[2], a[2]);
wire [2:0] bf;
buf BF0 (bf[0], a[0]),
BF1 (bf[1], a[1]),
BF2 (bf[2], a[2]);
// verilator lint_off IMPLICIT
not #(0.108) NT0 (nt0, a[0]);
@ -29,6 +30,11 @@ module t (/*AUTOARG*/
xnor (xn0, a[0], b[0], b[2]);
// verilator lint_on IMPLICIT
wire [2:0] bfm;
buf BFM (bfm[0], bfm[1], bfm[2], a[0]);
wire [2:0] ntm;
not NTM (ntm[0], ntm[1], ntm[2], a[0]);
parameter BITS=32;
wire [BITS-1:0] ba;
buf BARRAY [BITS-1:0] (ba, a);
@ -85,6 +91,8 @@ module t (/*AUTOARG*/
a <= 32'h529ab56f;
b <= 32'h7835a237;
if (bf !== 3'b100) $stop;
if (bfm != 3'b000) $stop;
if (ntm != 3'b111) $stop;
if (nt0 !== 1'b1) $stop;
if (an0 !== 1'b0) $stop;
if (nd0 !== 1'b1) $stop;
@ -96,6 +104,8 @@ module t (/*AUTOARG*/
end
if (cyc==3) begin
if (bf !== 3'b111) $stop;
if (bfm != 3'b111) $stop;
if (ntm != 3'b000) $stop;
if (nt0 !== 1'b0) $stop;
if (an0 !== 1'b1) $stop;
if (nd0 !== 1'b0) $stop;

4
test_regress/t/t_gate_delay_unsup.out
View File

@ -1,5 +1,5 @@
%Warning-RISEFALLDLY: t/t_gate_basic.v:25:12: Unsupported: rising/falling/turn-off delays. Using the first delay
25 | nand #(2,3) ND0 (nd0, a[0], b[0], b[1]);
%Warning-RISEFALLDLY: t/t_gate_basic.v:26:12: Unsupported: rising/falling/turn-off delays. Using the first delay
26 | nand #(2,3) ND0 (nd0, a[0], b[0], b[1]);
| ^
... For warning description see https://verilator.org/warn/RISEFALLDLY?v=latest
... Use "/* verilator lint_off RISEFALLDLY */" and lint_on around source to disable this message.