github/verilator
1
0
Fork 1
mirror of https://github.com/verilator/verilator.git synced 2025-01-22 14:24:18 +00:00
Code Issues Packages Projects Releases Wiki Activity

Tests (#3230)

Browse Source
This commit is contained in:
Wilson Snyder 2021-12-06 21:27:32 -05:00
parent 7b119a594f
commit 41f29d2ce3
1 changed files with 17 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
test_regress/t/t_foreach.v
View File

@ -16,6 +16,8 @@ module t (/*AUTOARG*/);
reg [2:1] [4:3] array [5:6] [7:8]; reg [2:1] [4:3] array [5:6] [7:8];
reg [1:2] [3:4] larray [6:5] [8:7]; reg [1:2] [3:4] larray [6:5] [8:7];
bit [31:0] depth1_array [0:0]; bit [31:0] depth1_array [0:0];
int oned [3:1];
int twod [3:1][9:8];
typedef struct packed { typedef struct packed {
reg [1:0] [63:0] subarray; reg [1:0] [63:0] subarray;
@ -110,6 +112,21 @@ module t (/*AUTOARG*/);
`checkh(add, 'h19); `checkh(add, 'h19);
`endif `endif
add = 0;
foreach (oned[i]) begin
++add;
break;
end
`checkh(add, 1); // 9
add = 0;
foreach (twod[i, j]) begin
++add;
break;
end
`checkh(add, 3); // 3,9 3,9, 3,9
// Although many simulators also do just "0,0". IEEE not clear - should we warn?.
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end