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Fix minor output spacing issues.

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This commit is contained in:
Wilson Snyder 2019-10-29 22:57:25 -04:00
parent 974bf1d643
commit 40bdd85a07
5 changed files with 22 additions and 22 deletions
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1
MANIFEST.SKIP
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@ -1,3 +1,4 @@
\.clang-format
\.clang-tidy
\.git/
\.git$

2
bin/verilator
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@ -1823,7 +1823,7 @@ This is an example similar to the above, but using SystemC.
cat >sc_main.cpp <<'EOF'
#include "Vour.h"
int sc_main(int argc, char **argv) {
int sc_main(int argc, char** argv) {
Verilated::commandArgs(argc, argv);
sc_clock clk ("clk", 10, 0.5, 3, true);
Vour* top;

6
nodist/fuzzer/wrapper.cpp
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@ -19,8 +19,8 @@
// This does slow down the execution to some degree but makes the results
// more reliable.
int main(int argc, char **argv, char **envp) {
int main(int argc, char** argv, char** envp) {
auto r = system("rm -rf obj_dir");
assert(r==0);
return execve("../../bin/verilator_bin",argv,envp);
assert(r == 0);
return execve("../../bin/verilator_bin", argv, envp);
}

21
src/V3EmitC.cpp
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@ -528,16 +528,16 @@ public:
virtual void visit(AstStop* nodep) {
puts("VL_STOP_MT(");
putsQuoted(protect(nodep->fileline()->filename()));
puts(",");
puts(", ");
puts(cvtToStr(nodep->fileline()->lineno()));
puts(",\"\");\n");
puts(", \"\");\n");
}
virtual void visit(AstFinish* nodep) {
puts("VL_FINISH_MT(");
putsQuoted(protect(nodep->fileline()->filename()));
puts(",");
puts(", ");
puts(cvtToStr(nodep->fileline()->lineno()));
puts(",\"\");\n");
puts(", \"\");\n");
}
virtual void visit(AstText* nodep) {
if (nodep->tracking() || m_trackText) {
@ -2138,7 +2138,7 @@ void EmitCImp::emitSettleLoop(const std::string& eval_call, bool initial) {
puts( "Verilated::debug(1);\n");
puts( "__Vchange = "+protect("_change_request")+"(vlSymsp);\n");
puts( "Verilated::debug(__Vsaved_debug);\n");
puts( "VL_FATAL_MT(__FILE__,__LINE__,__FILE__,\"Verilated model didn't ");
puts( "VL_FATAL_MT(__FILE__, __LINE__, __FILE__, \"Verilated model didn't ");
if (initial) puts("DC ");
puts( "converge\");\n");
puts( "} else {\n");
@ -2652,13 +2652,13 @@ void EmitCImp::emitInt(AstNodeModule* modp) {
puts("/// The special name "" may be used to make a wrapper with a\n");
puts("/// single model invisible with respect to DPI scope names.\n");
}
puts(modClassName(modp)+"(const char* name=\"TOP\");\n");
puts(modClassName(modp)+"(const char* name = \"TOP\");\n");
if (modp->isTop()) puts("/// Destroy the model; called (often implicitly) by application code\n");
puts("~"+modClassName(modp)+"();\n");
}
if (v3Global.opt.trace() && modp->isTop()) {
puts("/// Trace signals in the model; called by application code\n");
puts("void trace("+v3Global.opt.traceClassBase()+"C* tfp, int levels, int options=0);\n");
puts("void trace("+v3Global.opt.traceClassBase()+"C* tfp, int levels, int options = 0);\n");
if (optSystemC()) {
puts("/// SC tracing; avoid overloaded virtual function lint warning\n");
puts("virtual void trace(sc_trace_file* tfp) const { ::sc_core::sc_module::trace(tfp); }\n");
@ -2892,7 +2892,8 @@ class EmitCTrace : EmitCStmts {
puts(topClassName()+"* t = ("+topClassName()+"*)userthis;\n");
puts(EmitCBaseVisitor::symClassVar()+" = t->__VlSymsp; // Setup global symbol table\n");
puts("if (!Verilated::calcUnusedSigs()) {\n");
puts( "VL_FATAL_MT(__FILE__,__LINE__,__FILE__,\"Turning on wave traces requires Verilated::traceEverOn(true) call before time 0.\");\n");
puts( "VL_FATAL_MT(__FILE__, __LINE__, __FILE__,\n");
puts( " \"Turning on wave traces requires Verilated::traceEverOn(true) call before time 0.\");\n");
puts("}\n");
puts("vcdp->scopeEscape(' ');\n");
puts("t->"+protect("traceInitThis")+"(vlSymsp, vcdp, code);\n");
@ -2974,7 +2975,7 @@ class EmitCTrace : EmitCStmts {
if (nodep->declDirection().isInoutish()) puts(",FST_VD_INOUT");
else if (nodep->declDirection().isWritable()) puts(",FST_VD_OUTPUT");
else if (nodep->declDirection().isNonOutput()) puts(",FST_VD_INPUT");
else puts(",FST_VD_IMPLICIT");
else puts(", FST_VD_IMPLICIT");
//
// fstVarType
AstVarType vartype = nodep->varType();
@ -3165,7 +3166,7 @@ class EmitCTrace : EmitCStmts {
if (nodep->symProlog()) puts(EmitCBaseVisitor::symTopAssign()+"\n");
puts("int c=code;\n");
puts("int c = code;\n");
puts("if (0 && vcdp && c) {} // Prevent unused\n");
if (nodep->funcType() == AstCFuncType::TRACE_INIT) {
puts("vcdp->module(vlSymsp->name()); // Setup signal names\n");

14
test_regress/driver.pl
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@ -1577,12 +1577,10 @@ sub _make_main {
print $fh "#include \"verilated_vcd_sc.h\"\n" if $self->{trace} && $self->{trace_format} eq 'vcd-sc';
print $fh "#include \"verilated_save.h\"\n" if $self->{savable};
print $fh "$VM_PREFIX * topp;\n";
print $fh "$VM_PREFIX* topp;\n";
if (!$self->sc) {
print $fh "vluint64_t main_time = false;\n";
print $fh "double sc_time_stamp() {\n";
print $fh " return main_time;\n";
print $fh "}\n";
print $fh "double sc_time_stamp() { return main_time; }\n";
}
if ($self->{savable}) {
@ -1608,13 +1606,13 @@ sub _make_main {
#### Main
if ($self->sc) {
print $fh "extern int sc_main(int argc, char **argv);\n";
print $fh "int sc_main(int argc, char **argv) {\n";
print $fh "extern int sc_main(int argc, char** argv);\n";
print $fh "int sc_main(int argc, char** argv) {\n";
print $fh " sc_signal<bool> fastclk;\n" if $self->{inputs}{fastclk};
print $fh " sc_signal<bool> clk;\n" if $self->{inputs}{clk};
print $fh " sc_time sim_time($self->{sim_time}, SC_NS);\n";
} else {
print $fh "int main(int argc, char **argv, char **env) {\n";
print $fh "int main(int argc, char** argv, char** env) {\n";
print $fh " double sim_time = $self->{sim_time};\n";
}
print $fh " Verilated::commandArgs(argc, argv);\n";
@ -1690,7 +1688,7 @@ sub _make_main {
}
print $fh " }\n";
print $fh " if (!Verilated::gotFinish()) {\n";
print $fh ' vl_fatal(__FILE__,__LINE__,"main", "%Error: Timeout; never got a $finish");',"\n";
print $fh ' vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish");',"\n";
print $fh " }\n";
print $fh " topp->final();\n";