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Fix select value too wide (#5148) (#5153).

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Co-authored-by: Dercury <dercury@qq.com>
This commit is contained in:
Wilson Snyder 2024-06-07 08:27:03 -04:00
parent 7c9fa8647c
commit 3f886f7c61
5 changed files with 47 additions and 1 deletions
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1
Changes
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@ -225,6 +225,7 @@ Verilator 5.020 2024-01-01
* Fix dynamic NBA conditions (#4773). [Krzysztof Bieganski, Antmicro Ltd.]
* Fix `V3Fork` stage to run only if `--timing` is set (#4778). [Krzysztof Bieganski, Antmicro Ltd.]
* Fix max multiply width and add runtime assertions if too small. (#4781)
* Fix select value too wide (#5148) (#5153). [Dercury]
Verilator 5.018 2023-10-30

1
docs/CONTRIBUTORS
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@ -35,6 +35,7 @@ David Ledger
David Metz
David Stanford
David Turner
Dercury
Don Williamson
Drew Ranck
Drew Taussig

2
src/V3Number.cpp
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@ -1891,7 +1891,7 @@ V3Number& V3Number::opSub(const V3Number& lhs, const V3Number& rhs) {
NUM_ASSERT_OP_ARGS2(lhs, rhs);
NUM_ASSERT_LOGIC_ARGS2(lhs, rhs);
if (lhs.isFourState() || rhs.isFourState()) return setAllBitsX();
V3Number negrhs(&rhs, rhs.width());
V3Number negrhs(&rhs, width());
negrhs.opNegate(rhs);
return opAdd(lhs, negrhs);
}

17
test_regress/t/t_select_width.pl Executable file
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@ -0,0 +1,17 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(linter => 1);
lint(
);
ok(1);
1;

27
test_regress/t/t_select_width.v Normal file
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@ -0,0 +1,27 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2024 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/
// Outputs
vlan,
// Inputs
clk, pkt_data
);
parameter WIDTH = 320;
input clk;
input [2559:0] pkt_data;
output reg [15:0] vlan;
always @(posedge clk) begin
// verilator lint_off WIDTHCONCAT
// verilator lint_off WIDTHTRUNC
vlan <= pkt_data[ { (WIDTH-12), 3'b0 } - 1 -: 16];
// verilator lint_on WIDTHCONCAT
// verilator lint_on WIDTHTRUNC
end
endmodule