Fix ENUMVALUE on typedef (#3777)

Changes

@@ -19,7 +19,7 @@ Verilator 5.003 devel
 * Support pre_randomize and post_randomize.
 * Support $timeunit and $timeprecision.
 * Support assignment expressions.
-* Add ENUMVALUE warning when value misused for enum (#726).
+* Add ENUMVALUE warning when value misused for enum (#726) (#3777).
 * Internal AST improvements, also affect XML format (#3721). [Geza Lore]
 * Change ENDLABEL from warning into an error.
 * Deprecate verilated_fst_sc.cpp and verilated_vcd_sc.cpp.

src/V3Width.cpp

@@ -1941,6 +1941,7 @@ private:
             // if (debug()) nodep->backp()->dumpTree("-  CastOutUpUp: ");
         }
         if (m_vup->final()) {
+            // if (debug()) nodep->dumpTree(cout, "-  CastFPit: ");
             iterateCheck(nodep, "value", nodep->fromp(), SELF, FINAL, nodep->fromp()->dtypep(),
                          EXTEND_EXP, false);
             AstNode* const underp = nodep->fromp()->unlinkFrBack();
@@ -6966,28 +6967,20 @@ private:
         toDtp = toDtp->skipRefToEnump();
         fromDtp = fromDtp->skipRefToEnump();
         if (toDtp == fromDtp) return COMPATIBLE;
-        const AstNodeDType* fromBaseDtp = fromDtp;
-        while (const AstPackArrayDType* const packp = VN_CAST(fromBaseDtp, PackArrayDType)) {
-            fromBaseDtp = packp->subDTypep();
-            while (const AstRefDType* const refp = VN_CAST(fromBaseDtp, RefDType)) {
-                fromBaseDtp = refp->refDTypep();
-            }
-        }
+
+        // UNSUP unpacked struct/unions (treated like BasicDType)
+        const AstNodeDType* fromBaseDtp = computeCastableBase(fromDtp);
         const bool fromNumericable = VN_IS(fromBaseDtp, BasicDType)
                                      || VN_IS(fromBaseDtp, EnumDType)
                                      || VN_IS(fromBaseDtp, NodeUOrStructDType);
 
-        const AstNodeDType* toBaseDtp = toDtp;
-        while (const AstPackArrayDType* const packp = VN_CAST(toBaseDtp, PackArrayDType)) {
-            toBaseDtp = packp->subDTypep();
-            while (const AstRefDType* const refp = VN_CAST(toBaseDtp, RefDType)) {
-                toBaseDtp = refp->refDTypep();
-            }
-        }
+        const AstNodeDType* toBaseDtp = computeCastableBase(toDtp);
         const bool toNumericable
             = VN_IS(toBaseDtp, BasicDType) || VN_IS(toBaseDtp, NodeUOrStructDType);
-        // UNSUP unpacked struct/unions (treated like BasicDType)
-        if (toNumericable) {
+
+        if (toBaseDtp == fromBaseDtp) {
+            return COMPATIBLE;
+        } else if (toNumericable) {
             if (fromNumericable) return COMPATIBLE;
         } else if (VN_IS(toDtp, EnumDType)) {
             if (VN_IS(fromBaseDtp, EnumDType) && toDtp->sameTree(fromDtp)) return ENUM_IMPLICIT;
@@ -7010,6 +7003,20 @@ private:
         }
         return castable;
     }
+    static const AstNodeDType* computeCastableBase(const AstNodeDType* nodep) {
+        while (true) {
+            if (const AstPackArrayDType* const packp = VN_CAST(nodep, PackArrayDType)) {
+                nodep = packp->subDTypep();
+                continue;
+            } else if (const AstNodeDType* const refp = nodep->skipRefToEnump()) {
+                if (refp != nodep) {
+                    nodep = refp;
+                    continue;
+                }
+            }
+            return nodep;
+        }
+    }
 
     //----------------------------------------------------------------------
     // METHODS - special type detection

test_regress/t/t_cast_param_logic.pl

@@ -0,0 +1,17 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    );
+
+ok(1);
+1;

test_regress/t/t_cast_param_logic.v

@@ -0,0 +1,20 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t
+  #(
+    parameter type data_t = logic
+    )
+   (
+    input data_t[7:0] in_data
+    );
+
+    typedef data_t[7:0] in_data_t;
+
+    in_data_t out_data;
+    always_comb out_data = in_data_t'(in_data);
+
+endmodule