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Internals: Sort EmitXml visitors. No functional change.

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This commit is contained in:
Wilson Snyder 2018-01-31 07:25:10 -05:00
parent b2322ae873
commit 3c7fef68c0
1 changed files with 10 additions and 10 deletions
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20
src/V3EmitXml.cpp
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@ -97,6 +97,15 @@ class EmitXmlFileVisitor : public AstNVisitor {
}
// VISITORS
virtual void visit(AstAssignW* nodep) {
outputTag(nodep, "contassign"); // IEEE: vpiContAssign
outputChildrenEnd(nodep, "contassign");
}
virtual void visit(AstCell* nodep) {
outputTag(nodep, "instance"); // IEEE: vpiInstance
puts(" defName="); putsQuoted(nodep->modName()); // IEEE vpiDefName
outputChildrenEnd(nodep, "instance");
}
virtual void visit(AstNetlist* nodep) {
puts("<netlist>\n");
nodep->iterateChildren(*this);
@ -108,11 +117,6 @@ class EmitXmlFileVisitor : public AstNVisitor {
puts(" topModule=\"1\""); // IEEE vpiTopModule
outputChildrenEnd(nodep, "");
}
virtual void visit(AstCell* nodep) {
outputTag(nodep, "instance"); // IEEE: vpiInstance
puts(" defName="); putsQuoted(nodep->modName()); // IEEE vpiDefName
outputChildrenEnd(nodep, "instance");
}
virtual void visit(AstPin* nodep) {
// What we call a pin in verilator is a port in the IEEE spec.
outputTag(nodep, "port"); // IEEE: vpiPort
@ -125,10 +129,6 @@ class EmitXmlFileVisitor : public AstNVisitor {
// Children includes vpiHighConn and vpiLowConn; we don't support port bits (yet?)
outputChildrenEnd(nodep, "port");
}
virtual void visit(AstAssignW* nodep) {
outputTag(nodep, "contassign"); // IEEE: vpiContAssign
outputChildrenEnd(nodep, "contassign");
}
// Data types
virtual void visit(AstBasicDType* nodep) {
@ -165,7 +165,7 @@ void V3EmitXml::emitxml() {
of.puts("<!-- DESCR" "IPTION: Verilator output: XML representation of netlist -->\n");
of.puts("<verilator_xml>\n");
{
stringstream sstr;
std::stringstream sstr;
FileLine::fileNameNumMapDumpXml(sstr);
of.puts(sstr.str());
}