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Internals: Sort EmitXml visitors. No functional change.
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@ -97,6 +97,15 @@ class EmitXmlFileVisitor : public AstNVisitor {
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}
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// VISITORS
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virtual void visit(AstAssignW* nodep) {
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outputTag(nodep, "contassign"); // IEEE: vpiContAssign
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outputChildrenEnd(nodep, "contassign");
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}
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virtual void visit(AstCell* nodep) {
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outputTag(nodep, "instance"); // IEEE: vpiInstance
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puts(" defName="); putsQuoted(nodep->modName()); // IEEE vpiDefName
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outputChildrenEnd(nodep, "instance");
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}
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virtual void visit(AstNetlist* nodep) {
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puts("<netlist>\n");
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nodep->iterateChildren(*this);
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@ -108,11 +117,6 @@ class EmitXmlFileVisitor : public AstNVisitor {
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puts(" topModule=\"1\""); // IEEE vpiTopModule
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outputChildrenEnd(nodep, "");
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}
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virtual void visit(AstCell* nodep) {
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outputTag(nodep, "instance"); // IEEE: vpiInstance
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puts(" defName="); putsQuoted(nodep->modName()); // IEEE vpiDefName
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outputChildrenEnd(nodep, "instance");
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}
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virtual void visit(AstPin* nodep) {
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// What we call a pin in verilator is a port in the IEEE spec.
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outputTag(nodep, "port"); // IEEE: vpiPort
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@ -125,10 +129,6 @@ class EmitXmlFileVisitor : public AstNVisitor {
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// Children includes vpiHighConn and vpiLowConn; we don't support port bits (yet?)
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outputChildrenEnd(nodep, "port");
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}
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virtual void visit(AstAssignW* nodep) {
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outputTag(nodep, "contassign"); // IEEE: vpiContAssign
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outputChildrenEnd(nodep, "contassign");
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}
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// Data types
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virtual void visit(AstBasicDType* nodep) {
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@ -165,7 +165,7 @@ void V3EmitXml::emitxml() {
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of.puts("<!-- DESCR" "IPTION: Verilator output: XML representation of netlist -->\n");
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of.puts("<verilator_xml>\n");
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{
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stringstream sstr;
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std::stringstream sstr;
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FileLine::fileNameNumMapDumpXml(sstr);
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of.puts(sstr.str());
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}
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