diff --git a/Changes b/Changes
index 57f7c9fbf..fe5ad5f31 100644
--- a/Changes
+++ b/Changes
@@ -8,6 +8,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ***   Support string compare, icompare, ato* methods, bug1606. [Yutetsu TAKATSUKASA]
 
+****  Ignore `uselib to end-of-line, bug1634. [Frederic Antonin]
+
 ****  Update FST trace API for better performance.
 
 ****  Fix little endian cell ranges, bug1631. [Julien Margetts]
diff --git a/bin/verilator b/bin/verilator
index 3b5f43a87..1a99f5b3f 100755
--- a/bin/verilator
+++ b/bin/verilator
@@ -3316,7 +3316,7 @@ that Verilator will print a list of known scopes to help your debugging.
 
 =head2 Floating Point
 
-Floating Point (real) numbers are supported.
+Short floating point (shortreal) numbers are converted to real.
 
 =head2 Latches
 
@@ -3506,6 +3506,11 @@ Assignment patterns with order based, default, constant integer (array) or
 member identifier (struct/union) keys are supported.  Data type keys and
 keys which are computed from a constant expression are not supported.
 
+=item `uselib
+
+Uselib, a vendor specific library specification method, is ignored along
+with anything following it until the end of that line.
+
 =item cast operator
 
 Casting is supported only between simple scalar types, signed and unsigned,
diff --git a/src/verilog.l b/src/verilog.l
index 3740b4736..0422f0007 100644
--- a/src/verilog.l
+++ b/src/verilog.l
@@ -931,6 +931,7 @@ vnum    {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
                                           FL_BRK; }  // Rest handled by preproc
   "`suppress_faults"                    { FL_FWD; FL_BRK; }  // Verilog-XL compatibility
   "`timescale"{ws}+[^\n\r]*             { FL_FWD; FL_BRK; }  // Verilog spec - not supported
+  "`uselib"{ws}+[^\n\r]*                { FL_FWD; FL_BRK; }  // Verilog-XL compatibility
 
   /* See also setLanguage below */
   "`begin_keywords"[ \t]*\"1364-1995\"          { FL_FWD; yy_push_state(V95); PARSEP->pushBeginKeywords(YY_START); FL_BRK; }
diff --git a/test_regress/t/t_mod_uselib.pl b/test_regress/t/t_mod_uselib.pl
new file mode 100755
index 000000000..a1d77d628
--- /dev/null
+++ b/test_regress/t/t_mod_uselib.pl
@@ -0,0 +1,16 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2010 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_mod_uselib.v b/test_regress/t/t_mod_uselib.v
new file mode 100644
index 000000000..8a97b958e
--- /dev/null
+++ b/test_regress/t/t_mod_uselib.v
@@ -0,0 +1,17 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2019 by Wilson Snyder.
+
+module t (/*AUTOARG*/);
+//   // `uselib {dir=<lib_diry> | file=<lib_file> | libext=<file_ext> | lib=<lib_name>
+`uselib libext=.v
+   s s ();
+endmodule
+
+module s;
+  initial begin
+     $write("*-* All Finished *-*\n");
+     $finish;
+   end
+endmodule