diff --git a/test_regress/t/t_timescale_lint.pl b/test_regress/t/t_timescale_lint.pl
new file mode 100755
index 000000000..051f08f78
--- /dev/null
+++ b/test_regress/t/t_timescale_lint.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2008 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    verilator_flags2 => ["--lint-only --timescale-override 1ns/1ns"],
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_timescale_lint.v b/test_regress/t/t_timescale_lint.v
new file mode 100644
index 000000000..ae23c49dc
--- /dev/null
+++ b/test_regress/t/t_timescale_lint.v
@@ -0,0 +1,18 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under The Creative Commons Public Domain, for
+// any use, without warranty, 2020 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module pre_no_ts;
+endmodule
+
+`timescale 1ns/1ns
+
+module t;
+   pre_no_ts pre_no_ts();
+   post_no_ts pst_no_ts();
+endmodule
+
+module post_no_ts;
+endmodule