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Remove duplicate stop ignored messages

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This commit is contained in:
Wilson Snyder 2024-03-22 19:35:42 -04:00
parent f767f0cfaa
commit 38ad328956
2 changed files with 6 additions and 4 deletions
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9
include/verilated.cpp
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@ -169,9 +169,12 @@ void vl_stop_maybe(const char* filename, int linenum, const char* hier, bool may
Verilated::threadContextp()->errorCountInc();
if (maybe
&& Verilated::threadContextp()->errorCount() < Verilated::threadContextp()->errorLimit()) {
VL_PRINTF( // Not VL_PRINTF_MT, already on main thread
"-Info: %s:%d: %s\n", filename, linenum,
"Verilog $stop, ignored due to +verilator+error+limit");
// Do just once when cross error limit
if (Verilated::threadContextp()->errorCount() == 1) {
VL_PRINTF( // Not VL_PRINTF_MT, already on main thread
"-Info: %s:%d: %s\n", filename, linenum,
"Verilog $stop, ignored due to +verilator+error+limit");
}
} else {
vl_stop(filename, linenum, hier);
}

1
test_regress/t/t_runflag_errorlimit_bad.out
View File

@ -1,7 +1,6 @@
[0] %Error: t_runflag_errorlimit_bad.v:9: Assertion failed in top.t: One
-Info: t/t_runflag_errorlimit_bad.v:9: Verilog $stop, ignored due to +verilator+error+limit
[0] %Error: t_runflag_errorlimit_bad.v:10: Assertion failed in top.t: Two
-Info: t/t_runflag_errorlimit_bad.v:10: Verilog $stop, ignored due to +verilator+error+limit
[0] %Error: t_runflag_errorlimit_bad.v:11: Assertion failed in top.t: Three
%Error: t/t_runflag_errorlimit_bad.v:11: Verilog $stop
Aborting...