From 386f0a75df3899ba82d082204ddc02f9ccbc6f92 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Wed, 16 May 2007 19:27:29 +0000 Subject: [PATCH] Support automatic and additional v2k timing statements git-svn-id: file://localhost/svn/verilator/trunk/verilator@924 77ca24e4-aefa-0310-84f0-b9a241c72d87 --- src/verilog.l | 32 ++++++++++++++++---------------- src/verilog.y | 32 ++++++++++++++++++++------------ 2 files changed, 36 insertions(+), 28 deletions(-) diff --git a/src/verilog.l b/src/verilog.l index 6537f46b3..3f8cca1b3 100644 --- a/src/verilog.l +++ b/src/verilog.l @@ -274,30 +274,30 @@ escid \\[^ \t\f\r\n]+ "$signed" {yylval.fileline = CRELINE(); return yD_SIGNED;} "$unsigned" {yylval.fileline = CRELINE(); return yD_UNSIGNED;} /* Keywords */ + "automatic" {yylval.fileline = CRELINE(); return yAUTOMATIC;} "endgenerate" {yylval.fileline = CRELINE(); return yENDGENERATE;} "generate" {yylval.fileline = CRELINE(); return yGENERATE;} "genvar" {yylval.fileline = CRELINE(); return yGENVAR;} + "ifnone" {yylval.fileline = CRELINE(); return yaTIMINGSPEC;} "localparam" {yylval.fileline = CRELINE(); return yLOCALPARAM;} + "noshowcancelled" {yylval.fileline = CRELINE(); return yaTIMINGSPEC;} + "pulsestyle_ondetect" {yylval.fileline = CRELINE(); return yaTIMINGSPEC;} + "pulsestyle_onevent" {yylval.fileline = CRELINE(); return yaTIMINGSPEC;} + "showcancelled" {yylval.fileline = CRELINE(); return yaTIMINGSPEC;} "signed" {yylval.fileline = CRELINE(); return ySIGNED;} "unsigned" {yylval.fileline = CRELINE(); return yUNSIGNED;} /* Special errors */ - "include" {yyerrorf("Unsupported: Verilog 2001 reserved word not implemented; probably you want `include instead: %s",yytext);} + "include" {yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented; probably you want `include instead: %s",yytext);} /* Generic unsupported warnings */ - "automatic" {yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);} - "cell" {yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);} - "config" {yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);} - "design" {yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);} - "endconfig" {yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);} - "ifnone" {yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);} - "incdir" {yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);} - "instance" {yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);} - "liblist" {yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);} - "library" {yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);} - "noshowcancelled" {yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);} - "pulsestyle_ondetect" {yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);} - "pulsestyle_onevent" {yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);} - "showcancelled" {yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);} - "use" {yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);} + "cell" {yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext);} + "config" {yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext);} + "design" {yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext);} + "endconfig" {yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext);} + "incdir" {yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext);} + "instance" {yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext);} + "liblist" {yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext);} + "library" {yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext);} + "use" {yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext);} } /* Verilog 2005 */ diff --git a/src/verilog.y b/src/verilog.y index 030d3583a..d286e076f 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -148,6 +148,7 @@ class AstSenTree; %token yAND "and" %token yASSERT "assert" %token yASSIGN "assign" +%token yAUTOMATIC "automatic" %token yBEGIN "begin" %token yBUF "buf" %token yCASE "case" @@ -302,6 +303,7 @@ class AstSenTree; %type instnameParen %type cellpinList cellpinItList cellpinItemE instparamListE %type defpList defpOne +%type sensitivity %type sensitivityE %type senList senitem senitemEdge %type stmtBlock stmtList stmt labeledStmt stateCaseForIf @@ -414,12 +416,12 @@ regsigList: regsig { $$ = $1; } portV2kDecl: varRESET varInput varSignedE v2kNetDeclE regrangeE portV2kSig { $$ = $6; } | varRESET varInout varSignedE v2kNetDeclE regrangeE portV2kSig { $$ = $6; } - | varRESET varOutput varSignedE v2kVarDecl regrangeE portV2kSig { $$ = $6; } + | varRESET varOutput varSignedE v2kVarDeclE regrangeE portV2kSig { $$ = $6; } ; -ioDecl: varRESET varInput varSignedE v2kVarDecl regrangeE sigList ';' { $$ = $6; } - | varRESET varInout varSignedE v2kVarDecl regrangeE sigList ';' { $$ = $6; } - | varRESET varOutput varSignedE v2kVarDecl regrangeE sigList ';' { $$ = $6; } +ioDecl: varRESET varInput varSignedE v2kVarDeclE regrangeE sigList ';' { $$ = $6; } + | varRESET varInout varSignedE v2kVarDeclE regrangeE sigList ';' { $$ = $6; } + | varRESET varOutput varSignedE v2kVarDeclE regrangeE sigList ';' { $$ = $6; } ; varDecl: varRESET varReg varSignedE regrangeE regsigList ';' { $$ = $5; } @@ -465,7 +467,7 @@ v2kNetDeclE: /*empty*/ { } | varNet { } ; -v2kVarDecl: v2kNetDeclE { } +v2kVarDeclE: v2kNetDeclE { } | varReg { } ; @@ -707,7 +709,9 @@ cellpinItemE: /* empty: ',,' is legal */ { $$ = NULL; V3Parse::s_pinNum++; } // Sensitivity lists sensitivityE: /* empty */ { $$ = NULL; } - | '@' '(' senList ')' { $$ = new AstSenTree($1,$3); } + | sensitivity { $$ = $1; } + +sensitivity: '@' '(' senList ')' { $$ = new AstSenTree($1,$3); } | '@' senitem { $$ = new AstSenTree($1,$2); } | '@' '(' '*' ')' { $$ = NULL; $2->v3error("Use @*. always @ (*) to be depreciated in Verilog 2005.\n"); } | '@' '*' { $$ = NULL; } /* Verilog 2001 */ @@ -831,14 +835,18 @@ taskRef: idDotted { $$ = new AstTaskRef(CRELINE(),new AstParseRef($1->fileli funcRef: idDotted '(' exprList ')' { $$ = new AstFuncRef($2,new AstParseRef($1->fileline(), AstParseRefExp::FUNC, $1), $3); } ; -taskDecl: yTASK yaID ';' stmtBlock yENDTASK { $$ = new AstTask ($1,*$2,$4);} - | yTASK yaID ';' funcVarList stmtBlock yENDTASK { $$ = new AstTask ($1,*$2,$4); $4->addNextNull($5); } +taskDecl: yTASK taskAutoE yaID ';' stmtBlock yENDTASK { $$ = new AstTask ($1,*$3,$5);} + | yTASK taskAutoE yaID ';' funcVarList stmtBlock yENDTASK { $$ = new AstTask ($1,*$3,$5); $5->addNextNull($6); } ; -funcDecl: yFUNCTION funcTypeE yaID ';' funcBody yENDFUNCTION { $$ = new AstFunc ($1,*$3,$5,$2); } - | yFUNCTION ySIGNED funcTypeE yaID ';' funcBody yENDFUNCTION { $$ = new AstFunc ($1,*$4,$6,$3); $$->isSigned(true); } - | yFUNCTION funcTypeE yaID yVL_ISOLATE_ASSIGNMENTS ';' funcBody yENDFUNCTION { $$ = new AstFunc ($1,*$3,$6,$2); $$->attrIsolateAssign(true);} - | yFUNCTION ySIGNED funcTypeE yaID yVL_ISOLATE_ASSIGNMENTS ';' funcBody yENDFUNCTION { $$ = new AstFunc ($1,*$4,$7,$3); $$->attrIsolateAssign(true); $$->isSigned(true); } +funcDecl: yFUNCTION taskAutoE funcTypeE yaID ';' funcBody yENDFUNCTION { $$ = new AstFunc ($1,*$4,$6,$3); } + | yFUNCTION taskAutoE ySIGNED funcTypeE yaID ';' funcBody yENDFUNCTION { $$ = new AstFunc ($1,*$5,$7,$4); $$->isSigned(true); } + | yFUNCTION taskAutoE funcTypeE yaID yVL_ISOLATE_ASSIGNMENTS ';' funcBody yENDFUNCTION { $$ = new AstFunc ($1,*$4,$7,$3); $$->attrIsolateAssign(true);} + | yFUNCTION taskAutoE ySIGNED funcTypeE yaID yVL_ISOLATE_ASSIGNMENTS ';' funcBody yENDFUNCTION { $$ = new AstFunc ($1,*$5,$8,$4); $$->attrIsolateAssign(true); $$->isSigned(true); } + ; + +taskAutoE: /* empty */ { } + | yAUTOMATIC { } ; funcBody: funcVarList stmtBlock { $$ = $1;$1->addNextNull($2); }