diff --git a/.gitignore b/.gitignore
index fdc4102ff..04caf81c8 100644
--- a/.gitignore
+++ b/.gitignore
@@ -6,6 +6,7 @@
 *.info
 *.log
 *.1
+.*.swp
 *.tmp
 *.tex
 /Makefile
diff --git a/Changes b/Changes
index 24c67f992..6d2c1ded2 100644
--- a/Changes
+++ b/Changes
@@ -14,11 +14,13 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ***  Support "reg [1:0][1:0][1:0]" and "reg x [3][2]", bug176.  [Byron Bradley]
 
-***  Support declarations in loop initializers, bug172.  [by Bryon Bradley]
+***  Support declarations in loop initializers, bug172.  [by Byron Bradley]
 
 ***  Add VARHIDDEN warning when signal name hides module name.
 
-**** Fix Verilator core dump on wide integer divides, bug178. [Bryon Bradley]
+**** Support optional cell parenthesis, bug179. [by Byron Bradley]
+
+**** Fix Verilator core dump on wide integer divides, bug178. [Byron Bradley]
 
 * Verilator 3.720 2009/10/26
 
diff --git a/MANIFEST.SKIP b/MANIFEST.SKIP
index c4e63f689..6866427d1 100644
--- a/MANIFEST.SKIP
+++ b/MANIFEST.SKIP
@@ -8,6 +8,7 @@
 \.tar\.
 .*\.tgz
 .*\.log
+\..*\.swp
 .*\.tmp
 .*\.tex
 .*\.key
diff --git a/internals.pod b/internals.pod
index a3af3a9ae..96cb9bf53 100644
--- a/internals.pod
+++ b/internals.pod
@@ -22,8 +22,7 @@ Generally what would you do to add a new feature?
 
 File a bug (if there isn't already) so others know what you're working on.
 
-Make a testcase in the test_regress/t/t_EXAMPLE format, there's notes on
-this in the forum and in the verilator.txt manual.
+Make a testcase in the test_regress/t/t_EXAMPLE format, see TESTING Below.
 
 If grammar changes are needed, look at the git version of VerilogPerl's
 src/VParseGrammar.y, as this grammar supports the full SystemVerilog
@@ -95,6 +94,13 @@ variable is an output.
 
 =back
 
+=head1 TESTING
+
+To write a test see notes in the forum and in the verilator.txt manual.
+
+Note you can run the regression tests in parallel; see the
+test_regress/driver.pl script -j flag.
+
 =head1 VISITOR FUNCTIONS
 
 =head2 Passing Variables
diff --git a/src/verilog.y b/src/verilog.y
index 3aa77c856..b55f87984 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -644,6 +644,9 @@ modFront<modulep>:
 parameter_value_assignmentE<pinp>:	// IEEE: [ parameter_value_assignment ]
 		/* empty */				{ $$ = NULL; }
 	|	'#' '(' cellpinList ')'			{ $$ = $3; }
+	//			// Parentheses are optional around a single parameter
+	|	'#' yaINTNUM				{ $$ = new AstPin($1,1,"",new AstConst($1,*$2)); }
+	|	'#' idClassSel				{ $$ = new AstPin($1,1,"",$2); }
 	//			// Not needed in Verilator:
 	//			// Side effect of combining *_instantiations
 	//			// '#' delay_value	{ UNSUP }
diff --git a/test_regress/t/t_param_no_parentheses.pl b/test_regress/t/t_param_no_parentheses.pl
new file mode 100755
index 000000000..7058e622f
--- /dev/null
+++ b/test_regress/t/t_param_no_parentheses.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_param_no_parentheses.v b/test_regress/t/t_param_no_parentheses.v
new file mode 100644
index 000000000..f992cbe4c
--- /dev/null
+++ b/test_regress/t/t_param_no_parentheses.v
@@ -0,0 +1,74 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2003 by Wilson Snyder.
+//
+// This is a copy of t_param.v with the parentheses around the module parameters
+// removed.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   parameter PAR = 3;
+
+   m1 #PAR m1();
+   m3 #PAR m3();
+   mnooverride #10 mno();
+
+   input clk;
+   integer cyc=1;
+   reg [4:0] bitsel;
+
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+      if (cyc==0) begin
+	 bitsel = 0;
+	 if (PAR[bitsel]!==1'b1) $stop;
+	 bitsel = 1;
+	 if (PAR[bitsel]!==1'b1) $stop;
+	 bitsel = 2;
+	 if (PAR[bitsel]!==1'b0) $stop;
+      end
+      if (cyc==1) begin
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+
+endmodule
+
+module m1;
+   localparam PAR1MINUS1 = PAR1DUP-2-1;
+   localparam PAR1DUP = PAR1+2;  // Check we propagate parameters properly
+   parameter PAR1 = 0;
+   m2 #PAR1MINUS1 m2 ();
+endmodule
+
+module m2;
+   parameter PAR2 = 10;
+   initial begin
+      $display("%x",PAR2);
+      if (PAR2 !== 2) $stop;
+   end
+endmodule
+
+module m3;
+   localparam LOC = 13;
+   parameter PAR = 10;
+   initial begin
+      $display("%x %x",LOC,PAR);
+      if (LOC !== 13) $stop;
+      if (PAR !== 3) $stop;
+   end
+endmodule
+
+module mnooverride;
+   localparam LOC = 13;
+   parameter PAR = 10;
+   initial begin
+      $display("%x %x",LOC,PAR);
+      if (LOC !== 13) $stop;
+      if (PAR !== 10) $stop;
+   end
+endmodule