Fix false LIFETIME warning on repeat in fork-join (#5456).

Changes

@@ -247,9 +247,10 @@ Verilator 5.024 2024-04-05
 * Fix preprocessor to respect strings in joins (#5007).
 * Fix tracing class parameters (#5014).
 * Fix memory leaks (#5016). [Geza Lore]
-* Fix $readmem with missing newline (#5019). [Josse Van Delm]
+* Fix `$readmem` with missing newline (#5019). [Josse Van Delm]
 * Fix internal error on missing pattern key (#5023).
 * Fix tracing replicated hierarchical models (#5027).
+* Fix false LIFETIME warning on `repeat` in `fork-join` (#5456).
 
 
 Verilator 5.022 2024-02-24

src/V3LinkJump.cpp

@@ -202,12 +202,13 @@ class LinkJumpVisitor final : public VNVisitor {
         // Note var can be signed or unsigned based on original number.
         AstNodeExpr* const countp = nodep->countp()->unlinkFrBackWithNext();
         const string name = "__Vrepeat"s + cvtToStr(m_modRepeatNum++);
+        AstBegin* const beginp = new AstBegin{nodep->fileline(), "", nullptr, false, true};
         // Spec says value is integral, if negative is ignored
         AstVar* const varp
             = new AstVar{nodep->fileline(), VVarType::BLOCKTEMP, name, nodep->findSigned32DType()};
         varp->lifetime(VLifetime::AUTOMATIC);
         varp->usedLoopIdx(true);
-        m_modp->addStmtsp(varp);
+        beginp->addStmtsp(varp);
         AstNode* initsp = new AstAssign{
             nodep->fileline(), new AstVarRef{nodep->fileline(), varp, VAccess::WRITE}, countp};
         AstNode* const decp = new AstAssign{
@@ -222,8 +223,9 @@ class LinkJumpVisitor final : public VNVisitor {
         AstWhile* const whilep = new AstWhile{nodep->fileline(), condp, bodysp, decp};
         if (!m_unrollFull.isDefault()) whilep->unrollFull(m_unrollFull);
         m_unrollFull = VOptionBool::OPT_DEFAULT_FALSE;
-        initsp = initsp->addNext(whilep);
-        nodep->replaceWith(initsp);
+        beginp->addStmtsp(initsp);
+        beginp->addStmtsp(whilep);
+        nodep->replaceWith(beginp);
         VL_DO_DANGLING(nodep->deleteTree(), nodep);
     }
     void visit(AstWhile* nodep) override {

test_regress/t/t_debug_emitv.out

@@ -297,6 +297,8 @@ module Vt_debug_emitv_t;
             $display("%g", $acosh(r));
             $display("%g", $atanh(r));
             force sum = 'sha;
+            begin : unnamedblk1_1
+                integer signed [31:0]  __Vrepeat0;
                 __Vrepeat0 = 'sh2;
                 while ((__Vrepeat0 > 32'h0)) begin
                     if ((sum != 'sha)) begin
@@ -304,11 +306,11 @@ module Vt_debug_emitv_t;
                     end
                     __Vrepeat0 = (__Vrepeat0 - 32'h1);
                 end
+            end
             release sum;
         end
     end
     /*verilator public_flat_rw @(posedge clk) pubflat*/
-    integer signed [31:0]  __Vrepeat0;
 endmodule
 package Vt_debug_emitv___024unit;
     class Vt_debug_emitv_Cls;

test_regress/t/t_fork_repeat.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_flags2=["--binary"])
+
+test.execute()
+
+test.passes()

test_regress/t/t_fork_repeat.v

@@ -0,0 +1,34 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2024 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t(/*AUTOARG*/);
+   bit clk;
+
+   // Gen Clock
+   always #10
+     clk = ~clk;
+
+   initial begin
+      fork
+         begin
+            forever
+              @(posedge clk);
+         end
+         begin
+            repeat(10)
+              @(posedge clk);
+         end
+         begin
+            for(int i=0; i < 6; ++i)
+              @(posedge clk);
+         end
+      join_any
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule