Tests: Add alias tests as unsupported (#697)

test_regress/t/t_alias2_unsup.out

@@ -0,0 +1,4 @@
+%Error: t/t_alias2_unsup.v:39:4: Unsupported: alias statements
+   39 |    alias b = {a[3:0],a[7:4]};
+      |    ^~~~~
+%Error: Exiting due to

test_regress/t/t_alias2_unsup.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+lint(
+    fails => $Self->{vlt_all},
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_alias2_unsup.v

@@ -0,0 +1,41 @@
+// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias'
+//
+// Simple bi-directional alias test.
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2013 by Jeremy Bennett.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   // Values to swap and locations for the swapped values.
+   reg [31:0] x = 32'ha5a5a5a5;
+   wire [31:0] y;
+
+   testit testi_i (.a (x[7:0]),
+                   .b (y[31:24]));
+
+   always @ (posedge clk) begin
+      x <= {x[30:0],1'b0};
+      $write("x = %x, y = %x\n", x, y);
+
+      if (x[3:0] != 4'h0) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule
+
+
+// Swap the byte order of two args.
+module testit (input  wire [7:0] a,
+               output wire [7:0] b
+               );
+
+   alias b = {a[3:0],a[7:4]};
+
+endmodule

test_regress/t/t_alias_unsup.out

@@ -0,0 +1,4 @@
+%Error: t/t_alias_unsup.v:46:4: Unsupported: alias statements
+   46 |    alias {a[7:0],a[15:8],a[23:16],a[31:24]} = b;
+      |    ^~~~~
+%Error: Exiting due to

test_regress/t/t_alias_unsup.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+lint(
+    fails => $Self->{vlt_all},
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_alias_unsup.v

@@ -0,0 +1,58 @@
+// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias'
+//
+// Simple bi-directional alias test.
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2013 by Jeremy Bennett.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   // Values to swap and locations for the swapped values.
+   wire [31:0] x_fwd = 32'hdeadbeef;
+   wire [31:0] y_fwd;
+   wire [31:0] x_bwd;
+   wire [31:0] y_bwd = 32'hfeedface;
+
+   swap swap_fwd_i (.a (x_fwd),
+                    .b (y_fwd));
+   swap swap_bwd_i (.a (x_bwd),
+                    .b (y_bwd));
+
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write ("x_fwd = %x, y_fwd = %x\n", x_fwd, y_fwd);
+      $write ("x_bwd = %x, y_bwd = %x\n", x_bwd, y_bwd);
+`endif
+      if (y_fwd != 32'hefbeadde) $stop;
+      if (x_bwd == 32'hcefaedfe) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule
+
+
+// Swap the byte order of two args.
+module swap (
+             inout wire [31:0] a,
+             inout wire [31:0] b
+             );
+
+   alias {a[7:0],a[15:8],a[23:16],a[31:24]} = b;
+
+   // Equivalent to
+
+   // wire [31:0] a_prime;
+   // wire [31:0] b_prime;
+
+   // assign b_prime = {a[7:0],a[15:8],a[23:16],a[31:24]};
+   // assign {a_prime[7:0],a_prime[15:8],a_prime[23:16],a_prime[31:24]} = b;
+   // assign b = b_prime;
+   // assign a = a_prime;
+
+endmodule