From 317fe7a7870acac02d113bcdc4c3f43381bb129c Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Thu, 19 Jan 2023 17:11:09 -0500 Subject: [PATCH] Fix VL_CPU_RELAX on MIPS/Armel/s390/sparc (#3891) --- include/verilatedos.h | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/include/verilatedos.h b/include/verilatedos.h index 58fdb7143..0e30164a3 100644 --- a/include/verilatedos.h +++ b/include/verilatedos.h @@ -515,13 +515,24 @@ using ssize_t = uint32_t; ///< signed size_t; returned from read() # define VL_CPU_RELAX() asm volatile("rep; nop" ::: "memory") #elif defined(__ia64__) # define VL_CPU_RELAX() asm volatile("hint @pause" ::: "memory") +#elif defined(__armel__) || defined(__ARMEL__) // Arm, but broken, must be before __arm__ +# define VL_CPU_RELAX() asm volatile("nop" ::: "memory"); #elif defined(__aarch64__) || defined(__arm__) # define VL_CPU_RELAX() asm volatile("yield" ::: "memory") +#elif defined(__loongarch__) // LoongArch does not currently have yield/pause +# define VL_CPU_RELAX() asm volatile("nop" ::: "memory") +#elif defined(__mips64el__) || defined(__mips__) || defined(__mips64__) || defined(__mips64) +# define VL_CPU_RELAX() asm volatile("pause" ::: "memory") #elif defined(__powerpc64__) # define VL_CPU_RELAX() asm volatile("or 1, 1, 1; or 2, 2, 2;" ::: "memory") -#elif defined(__loongarch__) || defined(__riscv) -// LoongArch does not currently have a yield/pause instruction +#elif defined(__riscv) // RiscV does not currently have yield/pause, but one is proposed # define VL_CPU_RELAX() asm volatile("nop" ::: "memory") +#elif defined(__s390x__) +# define VL_CPU_RELAX() asm volatile("lr 0,0" ::: "memory") +#elif defined(__sparc__) +# define VL_CPU_RELAX() asm volatile("rd %%ccr, %%g0" ::: "memory") +#elif defined(VL_IGNORE_UNKNOWN_ARCH) +# define VL_CPU_RELAX() #else # error "Missing VL_CPU_RELAX() definition." #endif