Fix to not emit already waived warnings in waiver output (#4574) (#4818)

docs/CONTRIBUTORS

@@ -88,6 +88,7 @@ John Coiner
 John Demme
 John Wehle
 Jonathan Drolet
+Jonathan Schröter
 Jordan McConnon
 Jose Loyola
 Josep Sans

src/V3FileLine.cpp

@@ -411,7 +411,7 @@ void FileLine::v3errorEnd(std::ostringstream& sstr, const string& extra)
     } else if (!V3Error::s().errorContexted()) {
         nsstr << warnContextPrimary();
     }
-    if (!m_waive) V3Waiver::addEntry(V3Error::s().errorCode(), filename(), sstr.str());
+    if (!warnIsOff(V3Error::s().errorCode()) && !m_waive) V3Waiver::addEntry(V3Error::s().errorCode(), filename(), sstr.str());
     V3Error::v3errorEnd(nsstr, lstr.str());
 }
 

test_regress/t/t_waiveroutput.out

@@ -7,7 +7,4 @@
 //   2. Keep the waiver permanently if you are sure this is okay
 //   3. Keep the waiver temporarily to suppress the output
 
-// lint_off -rule WIDTHTRUNC -file "*t/t_waiveroutput.v" -match "Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '2'h3' generates 2 bits."
-
-// lint_off -rule UNUSEDSIGNAL -file "*t/t_waiveroutput.v" -match "Signal is not used: 'width_warn'"
-
+// No waivers needed - great!

test_regress/t/t_waiveroutput.pl

@@ -10,22 +10,16 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(vlt => 1);
 
-my $out_filename = "$Self->{obj_dir}/$Self->{name}_waiver_gen.vlt";
-my $waiver_filename = "$Self->{obj_dir}/$Self->{name}_waiver.vlt";
+my $out_filename = "$Self->{obj_dir}/$Self->{name}_waiver_gen.out";
+my $waiver_filename = "t/$Self->{name}.vlt";
+
+top_filename("t/t_waiveroutput.v");
 
 compile(
-    v_flags2 => ['--waiver-output', $out_filename],
-    fails => 1,
+    v_flags2 => [$waiver_filename, '--waiver-output', $out_filename],
     );
 
 files_identical("$out_filename", $Self->{golden_filename});
 
-file_sed($out_filename, $waiver_filename,
-         sub { s/\/\/ lint_off/lint_off/g; });
-
-compile(
-    v_flags2 => [$waiver_filename],
-    );
-
 ok(1);
 1;

test_regress/t/t_waiveroutput.v

@@ -5,6 +5,11 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module t_waiveroutput;
+   reg width_warn = 2'b11;  // Width warning - must be line 8
 
-   reg width_warn = 2'b11;  // Width warning - must be line 18
+   // verilator lint_off UNUSEDSIGNAL
+   // verilator lint_off WIDTHTRUNC
+   reg width_warn2 = 2'b11;
+   // verilator lint_on UNUSEDSIGNAL
+   // verilator lint_on WIDTHTRUNC
 endmodule

test_regress/t/t_waiveroutput.vlt

@@ -0,0 +1,9 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2020 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`verilator_config
+
+lint_off -rule WIDTH -file "*t/t_waiveroutput.v" -match "Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '2'h3' generates 2 bits."

test_regress/t/t_waiveroutput_wall.out

@@ -0,0 +1,10 @@
+// DESCRIPTION: Verilator output: Waivers generated with --waiver-output
+
+`verilator_config
+
+// Below you find suggested waivers. You have three options:
+//   1. Fix the reason for the linter warning
+//   2. Keep the waiver permanently if you are sure this is okay
+//   3. Keep the waiver temporarily to suppress the output
+
+// No waivers needed - great!

test_regress/t/t_waiveroutput_wall.pl

@@ -0,0 +1,25 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2012 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+my $out_filename = "$Self->{obj_dir}/$Self->{name}_waiver_gen.out";
+my $waiver_filename = "t/$Self->{name}.vlt";
+
+top_filename("t/t_waiveroutput.v");
+
+compile(
+    v_flags2 => ['-Wall', $waiver_filename, '--waiver-output', $out_filename],
+    );
+
+files_identical("$out_filename", $Self->{golden_filename});
+
+ok(1);
+1;

test_regress/t/t_waiveroutput_wall.vlt

@@ -0,0 +1,11 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2020 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`verilator_config
+
+lint_off -rule WIDTH -file "*t/t_waiveroutput.v" -match "Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '2'h3' generates 2 bits."
+
+lint_off -rule UNUSED -file "*t/t_waiveroutput.v" -match "Signal is not used: 'width_warn'"