github/verilator
1
0
Fork 1
mirror of https://github.com/verilator/verilator.git synced 2025-07-31 07:56:10 +00:00
Code Issues Packages Projects Releases Wiki Activity

Fix $ in filenames (#2768).

Browse Source
This commit is contained in:
Wilson Snyder 2021-01-26 20:10:27 -05:00
parent d891e5ac3a
commit 31223d4058
3 changed files with 42 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/V3Options.cpp
View File

@ -18,6 +18,7 @@
#include "verilatedos.h"
#include "V3Global.h"
#include "V3Ast.h"
#include "V3String.h"
#include "V3Os.h"
#include "V3Options.h"
@ -864,10 +865,10 @@ void V3Options::parseOpts(FileLine* fl, int argc, char** argv) {
}
// Default prefix to the filename
if (prefix() == "" && topModule() != "") m_prefix = string("V") + topModule();
if (prefix() == "" && vFilesList.size() >= 1) {
m_prefix = string("V") + V3Os::filenameNonExt(*(vFilesList.begin()));
}
if (prefix() == "" && topModule() != "")
m_prefix = string("V") + AstNode::encodeName(topModule());
if (prefix() == "" && vFilesList.size() >= 1)
m_prefix = string("V") + AstNode::encodeName(V3Os::filenameNonExt(*(vFilesList.begin())));
if (modPrefix() == "") m_modPrefix = prefix();
// Find files in makedir

25
test_regress/t/t_mod_dollar$.pl Executable file
View File

@ -0,0 +1,25 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2019 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt => 1);
# This doesn't use the general compile rule as we want to make sure we form
# prefix properly using post-escaped identifiers
run(cmd => ["../bin/verilator",
"--cc",
"--Mdir obj_vlt/t_mod_dollar",
"--exe --build --main",
't/t_mod_dollar$.v',
],
verilator_run => 1,
);
ok(1);
1;

12
test_regress/t/t_mod_dollar$.v Normal file
View File

@ -0,0 +1,12 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by engr248.
// SPDX-License-Identifier: CC0-1.0
module \foo$bar (/*AUTOARG*/);
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule