diff --git a/src/V3AstNodeDType.h b/src/V3AstNodeDType.h
index 3dc9d7d2c..18d121cb7 100644
--- a/src/V3AstNodeDType.h
+++ b/src/V3AstNodeDType.h
@@ -904,6 +904,7 @@ public:
     string cellName() const { return m_cellName; }
     void cellName(const string& name) { m_cellName = name; }
     string ifaceName() const { return m_ifaceName; }
+    string ifaceNameQ() const { return "'" + prettyName(ifaceName()) + "'"; }
     void ifaceName(const string& name) { m_ifaceName = name; }
     string modportName() const { return m_modportName; }
     AstIface* ifaceViaCellp() const;  // Use cellp or ifacep
diff --git a/src/V3LinkCells.cpp b/src/V3LinkCells.cpp
index c240cf76a..5667f8856 100644
--- a/src/V3LinkCells.cpp
+++ b/src/V3LinkCells.cpp
@@ -236,7 +236,7 @@ class LinkCellsVisitor final : public VNVisitor {
                 if (!nodep->cellp()) nodep->ifacep(VN_AS(modp, Iface));
             } else if (VN_IS(modp, NotFoundModule)) {  // Will error out later
             } else {
-                nodep->v3error("Non-interface used as an interface: " << nodep->prettyNameQ());
+                nodep->v3error("Non-interface used as an interface: " << nodep->ifaceNameQ());
             }
         }
         iterateChildren(nodep);
diff --git a/test_regress/t/t_interface_paren_missing_bad.v b/test_regress/t/t_interface_paren_missing_bad.v
index c1a9edae4..5a02d2ae1 100644
--- a/test_regress/t/t_interface_paren_missing_bad.v
+++ b/test_regress/t/t_interface_paren_missing_bad.v
@@ -1,11 +1,11 @@
 // DESCRIPTION: Verilator: Verilog Test module
 //
-// Interface instantiation without paranthesis
-//
 // This file ONLY is placed under the Creative Commons Public Domain, for
 // any use, without warranty, 2023 by Goekce Aydos.
 // SPDX-License-Identifier: CC0-1.0
 
+// Interface instantiation without parenthesis
+
 interface intf;
 endinterface