Tests: New struct tests. Merge from branch.

test_regress/t/t_struct_init.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} and $Self->unsupported("Verilator unsupported, bug181");
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;
+

test_regress/t/t_struct_init.v

@@ -0,0 +1,80 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2009 by Wilson Snyder.
+
+module t;
+
+   //Several simulators don't support this.
+   //typedef struct pack2;	// Forward declaration
+
+   typedef struct packed {
+      bit	b3;
+      bit	b2;
+      bit	b1;
+      bit	b0;
+   } b4_t;
+
+   typedef union packed {
+      bit [3:0]	quad0;
+      b4_t	quad1;
+   } q4_t;
+
+   typedef struct packed {
+      bit	msb;
+      q4_t	four;
+      bit	lsb;
+   } pack2_t;
+
+   typedef union packed {
+      pack2_t	pack2;
+      bit [5:0] pvec;
+      // Vector not allowed in packed structure: (Seems cheezy to disallow this)
+      //      bit	vec[6];
+      //      bit 	vec2d[2][3];
+   } pack3_t;
+
+   initial begin
+      pack3_t tsu;
+      tsu = 6'b100110;
+      if (tsu!=6'b100110) $stop;
+      if (tsu.pvec!=6'b100110) $stop;
+      if (tsu.pack2.msb != 1'b1) $stop;
+      if (tsu.pack2.lsb != 1'b0) $stop;
+      if (tsu.pack2.four.quad0  != 4'b0011) $stop;
+      if (tsu.pack2.four.quad1.b0 != 1'b1) $stop;
+      if (tsu.pack2.four.quad1.b1 != 1'b1) $stop;
+      if (tsu.pack2.four.quad1.b2 != 1'b0) $stop;
+      if (tsu.pack2.four.quad1.b3 != 1'b0) $stop;
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+   initial begin
+      $display("Need init fix\n");
+      $stop;
+   end
+//UNSUP   // Initialization
+//UNSUP   initial begin
+//UNSUP      b4_t q = '{1'b1, 1'b1, 1'b0, 1'b0};
+//UNSUP      if (q != 4'b1100) $stop;
+//UNSUP   end
+//UNSUP   initial begin
+//UNSUP      b4_t q = '{4{1'b1}};	// Repeats the {}
+//UNSUP      if (q != 4'b1111) $stop;
+//UNSUP   end
+//UNSUP   initial begin
+//UNSUP      b4_t q = '{b0:1'b1, b2:1'b1, b3:1'b1, b1:1'b0};
+//UNSUP      if (q != 4'b1101) $stop;
+//UNSUP   end
+//UNSUP   initial begin
+//UNSUP      b4_t q = '{default:1'b1};
+//UNSUP      if (q != 4'b1111) $stop;
+//UNSUP      q.b1 = 0;
+//UNSUP      if (q != 4'b1101) $stop;
+//UNSUP      {q.b3,q.b2} = 2'b10;
+//UNSUP      if (q != 4'b1001) $stop;
+//UNSUP   end
+
+endmodule

test_regress/t/t_struct_port.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} and $Self->unsupported("Verilator unsupported, bug181");
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;
+

test_regress/t/t_struct_port.v

@@ -0,0 +1,84 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2009 by Wilson Snyder.
+
+typedef struct packed {
+   bit 	       b9;
+   byte	       b1;
+   bit 	       b0;
+} pack_t;
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer 	cyc=0;
+   reg [63:0] 	crc;
+   reg [63:0] 	sum;
+
+   // Take CRC data and apply to testblock inputs
+   pack_t in;
+   always @* in = crc[10:0];
+
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   pack_t		out;			// From test of Test.v
+   // End of automatics
+
+   Test test (/*AUTOINST*/
+	      // Outputs
+	      .out			(out),
+	      // Inputs
+	      .in			(in));
+
+   // Aggregate outputs into a single result vector
+   wire [63:0] result = {54'h0, out};
+
+   // Test loop
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x in=%x result=%x\n",$time, cyc, crc, in, result);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+      sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+      if (cyc==0) begin
+	 // Setup
+	 crc <= 64'h5aef0c8d_d70a4497;
+	 sum <= 64'h0;
+      end
+      else if (cyc<10) begin
+	 sum <= 64'h0;
+      end
+      else if (cyc<90) begin
+      end
+      else if (cyc==99) begin
+	 $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+	 if (crc !== 64'hc77bb9b3784ea091) $stop;
+	 // What checksum will we end up with (above print should match)
+`define EXPECTED_SUM 64'h99c434d9b08c2a8a
+	 if (sum !== `EXPECTED_SUM) $stop;
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+
+endmodule
+
+module Test (
+	     input  pack_t in,
+	     output pack_t out);
+
+   always @* begin
+      out = in;
+      out.b1 = in.b1 + 1;
+      out.b0 = 1'b1;
+   end
+endmodule
+
+// Local Variables:                                                                                                          
+// verilog-typedef-regexp: "_t$"                                                                                             
+// End: