github/verilator
1
0
Fork 1
mirror of https://github.com/verilator/verilator.git synced 2025-01-19 12:54:02 +00:00
Code Issues Packages Projects Releases Wiki Activity

Tests: rename

Browse Source
This commit is contained in:
Wilson Snyder 2022-12-08 07:23:53 -05:00
parent 4b6e15d0eb
commit 2dc0053ea4
2 changed files with 1 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

0
test_regress/t/t_timing_bug3781.pl → test_regress/t/t_timing_dlyassign.pl
View File

1
test_regress/t/t_timing_bug3781.v → test_regress/t/t_timing_dlyassign.v
View File

@ -4,6 +4,7 @@
// any use, without warranty, 2022 by Antmicro Ltd.
// SPDX-License-Identifier: CC0-1.0
// bug3781
module t;
logic clk;
logic [7:0] data;