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Fix implicit nets when created after used
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@ -467,6 +467,9 @@ private:
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nodep->iterateChildren(*this);
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m_cellVarsp = NULL;
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}
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else if (m_idState==ID_PARAM) {
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nodep->iterateChildren(*this);
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}
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}
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// Parent module inherits child's publicity
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// This is done bottom up in the LinkBotupVisitor stage
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@ -509,14 +512,15 @@ private:
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if (nodep->op2p()) pinImplicitExprRecurse(nodep->op2p());
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if (nodep->op3p()) pinImplicitExprRecurse(nodep->op3p());
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if (nodep->op4p()) pinImplicitExprRecurse(nodep->op4p());
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if (nodep->nextp()) pinImplicitExprRecurse(nodep->nextp());
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}
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}
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virtual void visit(AstPin* nodep, AstNUser*) {
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// Pin: Link to submodule's pin
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// ONLY CALLED by AstCell during ID_RESOLVE state
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if (!m_cellVarsp) nodep->v3fatalSrc("Pin not under cell?\n");
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// ONLY CALLED by AstCell during ID_RESOLVE and ID_PARAM state
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if (m_idState==ID_RESOLVE && !nodep->modVarp()) {
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if (!m_cellVarsp) nodep->v3fatalSrc("Pin not under cell?\n");
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AstVar* refp = m_cellVarsp->findIdFlat(nodep->name())->castVar();
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if (!refp) {
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nodep->v3error("Pin not found: "<<nodep->prettyName());
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@ -525,13 +529,12 @@ private:
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} else {
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nodep->modVarp(refp);
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}
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nodep->iterateChildren(*this);
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}
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// Deal with implicit definitions
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if (m_idState==ID_RESOLVE && nodep->modVarp()
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&& !nodep->svImplicit()) { // SV 19.11.3: .name pins don't allow implicit decls
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// Deal with implicit definitions - do before ID_RESOLVE stage as may be referenced above declaration
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if (m_idState==ID_PARAM && !nodep->svImplicit()) { // SV 19.11.3: .name pins don't allow implicit decls
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pinImplicitExprRecurse(nodep->exprp());
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}
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nodep->iterateChildren(*this);
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}
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virtual void visit(AstAssignW* nodep, AstNUser*) {
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18
test_regress/t/t_gate_implicit.pl
Executable file
18
test_regress/t/t_gate_implicit.pl
Executable file
@ -0,0 +1,18 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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compile (
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);
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execute (
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check_finished=>1,
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);
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ok(1);
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1;
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80
test_regress/t/t_gate_implicit.v
Normal file
80
test_regress/t/t_gate_implicit.v
Normal file
@ -0,0 +1,80 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2009 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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reg [63:0] crc;
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reg [63:0] sum;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire RBL2; // From t of Test.v
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// End of automatics
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wire RWL1 = crc[2];
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wire RWL2 = crc[3];
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Test t (/*AUTOINST*/
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// Outputs
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.RBL2 (RBL2),
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// Inputs
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.RWL1 (RWL1),
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.RWL2 (RWL2));
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// Aggregate outputs into a single result vector
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wire [63:0] result = {63'h0, RBL2};
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
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if (cyc==0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= 64'h0;
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end
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else if (cyc<10) begin
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sum <= 64'h0;
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end
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else if (cyc<90) begin
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end
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else if (cyc==99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'hb6d6b86aa20a882a
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test (
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output RBL2,
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input RWL1, RWL2);
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// verilator lint_off IMPLICIT
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not I1 (RWL2_n, RWL2);
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bufif1 I2 (RBL2, n3, 1'b1);
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Mxor I3 (n3, RWL1, RWL2_n);
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// verilator lint_on IMPLICIT
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endmodule
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module Mxor (output out, input a, b);
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assign out = (a ^ b);
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endmodule
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