diff --git a/Changes b/Changes
index 0792518a2..5166dd8ab 100644
--- a/Changes
+++ b/Changes
@@ -9,6 +9,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 **    Support hierarchical Verilation (#2206). [Yutetsu TAKATSUKASA]
 
+****  Fix false DECLFILENAME on black-boxed modules (#2430). [Philipp Wagner]
+
 
 * Verilator 4.040 2020-08-15
 
diff --git a/src/V3LinkCells.cpp b/src/V3LinkCells.cpp
index df69692b1..e35c74bb6 100644
--- a/src/V3LinkCells.cpp
+++ b/src/V3LinkCells.cpp
@@ -201,6 +201,7 @@ private:
             UINFO(2, "Link Module: " << nodep << endl);
             if (nodep->fileline()->filebasenameNoExt() != nodep->prettyName()
                 && !v3Global.opt.isLibraryFile(nodep->fileline()->filename())
+                && !VN_IS(nodep, NotFoundModule)
                 && !nodep->recursiveClone() && !nodep->internal()) {
                 // We only complain once per file, otherwise library-like files
                 // have a huge mess of warnings
diff --git a/test_regress/t/t_lint_declfilename_bbox.pl b/test_regress/t/t_lint_declfilename_bbox.pl
new file mode 100755
index 000000000..f73da325a
--- /dev/null
+++ b/test_regress/t/t_lint_declfilename_bbox.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+lint(
+    verilator_flags2 => ["--lint-only -Wall"],
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_lint_declfilename_bbox.v b/test_regress/t/t_lint_declfilename_bbox.v
new file mode 100644
index 000000000..c9bea6e23
--- /dev/null
+++ b/test_regress/t/t_lint_declfilename_bbox.v
@@ -0,0 +1,13 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2010 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t_lint_declfilename_bbox ();
+   parameter IN = 0;
+   if (IN) begin
+      // Should not warn, see bug2430
+      BLACKBOXED bboxed ();
+   end
+endmodule