From 2aed499e00b42d789fe29e6c320b9f6af696ae85 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Tue, 5 Nov 2019 21:15:44 -0500 Subject: [PATCH] Fix detecting missing reg types, bug1570. --- Changes | 2 + src/V3Ast.h | 1 - src/V3Undriven.cpp | 4 +- src/verilog.y | 9 +- test_regress/t/t_cdc_async_bad.v | 2 +- test_regress/t/t_clocker.v | 6 +- test_regress/t/t_dedupe_clk_gate.v | 4 +- test_regress/t/t_dedupe_seq_logic.v | 4 +- test_regress/t/t_embed1_child.v | 4 +- test_regress/t/t_embed1_wrap.v | 10 +- test_regress/t/t_emit_memb_limit.pl | 4 +- test_regress/t/t_extend_class.v | 2 +- test_regress/t/t_func_unit.v | 6 +- test_regress/t/t_mem_slot.v | 2 +- test_regress/t/t_order_multidriven.v | 4 +- test_regress/t/t_struct_anon.v | 4 +- test_regress/t/t_trace_fst.out | 1212 +++++++++-------- test_regress/t/t_var_dup_bad.out | 1 + test_regress/t/t_var_pinsizes.v | 24 +- test_regress/t/t_wire_beh1364_bad.out | 13 + ..._wire_beh_bad.pl => t_wire_beh1364_bad.pl} | 0 test_regress/t/t_wire_beh1364_bad.v | 32 + test_regress/t/t_wire_beh1800_bad.out | 13 + test_regress/t/t_wire_beh1800_bad.pl | 19 + test_regress/t/t_wire_beh1800_bad.v | 32 + test_regress/t/t_wire_beh_bad.out | 9 - test_regress/t/t_wire_beh_bad.v | 14 - test_regress/t/t_wire_behp1364_bad.out | 13 + test_regress/t/t_wire_behp1364_bad.pl | 19 + test_regress/t/t_wire_behp1364_bad.v | 30 + test_regress/t/t_wire_behp1800_bad.out | 13 + test_regress/t/t_wire_behp1800_bad.pl | 19 + test_regress/t/t_wire_behp1800_bad.v | 30 + 33 files changed, 886 insertions(+), 675 deletions(-) create mode 100644 test_regress/t/t_wire_beh1364_bad.out rename test_regress/t/{t_wire_beh_bad.pl => t_wire_beh1364_bad.pl} (100%) create mode 100644 test_regress/t/t_wire_beh1364_bad.v create mode 100644 test_regress/t/t_wire_beh1800_bad.out create mode 100755 test_regress/t/t_wire_beh1800_bad.pl create mode 100644 test_regress/t/t_wire_beh1800_bad.v delete mode 100644 test_regress/t/t_wire_beh_bad.out delete mode 100644 test_regress/t/t_wire_beh_bad.v create mode 100644 test_regress/t/t_wire_behp1364_bad.out create mode 100755 test_regress/t/t_wire_behp1364_bad.pl create mode 100644 test_regress/t/t_wire_behp1364_bad.v create mode 100644 test_regress/t/t_wire_behp1800_bad.out create mode 100755 test_regress/t/t_wire_behp1800_bad.pl create mode 100644 test_regress/t/t_wire_behp1800_bad.v diff --git a/Changes b/Changes index eaeb01a25..59cdbf3f8 100644 --- a/Changes +++ b/Changes @@ -24,6 +24,8 @@ The contributors that suggested a given feature are shown in []. Thanks! **** Support quoted arguments in -f files, bug1535. [Yves Mathieu] +**** Fix detecting missing reg types, bug1570. [Jacko Dirks] + **** Fix multithreaded yield behavior when no work. [Patrick Stewart] **** Fix bad-syntax crashes, bug1548, bug1550-1553, bug1557-1560, bug1563, diff --git a/src/V3Ast.h b/src/V3Ast.h index e8bc544ac..7562e5120 100644 --- a/src/V3Ast.h +++ b/src/V3Ast.h @@ -601,7 +601,6 @@ public: bool isProcAssignable() const { return (m_e==GPARAM || m_e==LPARAM || m_e==GENVAR || m_e==VAR - || m_e==TRIWIRE || m_e==TRI0 || m_e==TRI1 || m_e==PORT || m_e==BLOCKTEMP || m_e==MODULETEMP || m_e==STMTTEMP || m_e==XTEMP || m_e==IFACEREF); } diff --git a/src/V3Undriven.cpp b/src/V3Undriven.cpp index 050c3b81e..e185e1692 100644 --- a/src/V3Undriven.cpp +++ b/src/V3Undriven.cpp @@ -331,7 +331,9 @@ private: // Any variable if (nodep->lvalue() && !VN_IS(nodep, VarXRef)) { // Ignore interface variables and similar ugly items - if (m_inProcAssign && !nodep->varp()->varType().isProcAssignable()) { + if (m_inProcAssign && !nodep->varp()->varType().isProcAssignable() + && !nodep->varp()->isDeclTyped() + && !nodep->varp()->isFuncLocal()) { nodep->v3warn(PROCASSWIRE, "Procedural assignment to wire, perhaps intended var" " (IEEE 2017 6.5): " +nodep->prettyNameQ()); diff --git a/src/verilog.y b/src/verilog.y index 72cd5f0f0..f3c82a578 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -121,12 +121,7 @@ public: fl->v3warn(ENDLABEL,"End label '"<<*endnamep<<"' does not match begin label '"<deleteTree(); m_varDTypep=NULL; } // It was cloned, so this is safe. m_varDTypep = dtypep; @@ -1306,7 +1301,7 @@ net_declaration: // IEEE: net_declaration - excluding implict ; net_declarationFront: // IEEE: beginning of net_declaration - net_declRESET net_type strengthSpecE net_scalaredE net_dataTypeE { VARDTYPE($5); } + net_declRESET net_type strengthSpecE net_scalaredE net_dataTypeE { VARDTYPE_NDECL($5); } //UNSUP net_declRESET yINTERCONNECT signingE rangeListE { VARNET($2); VARDTYPE(x); } ; diff --git a/test_regress/t/t_cdc_async_bad.v b/test_regress/t/t_cdc_async_bad.v index 1a5fbf805..679ffa81f 100644 --- a/test_regress/t/t_cdc_async_bad.v +++ b/test_regress/t/t_cdc_async_bad.v @@ -67,7 +67,7 @@ module Flop ( input clk, input d, input rst_n, - output q); + output logic q); always @ (posedge clk or negedge rst_n) begin if (!rst_n) q <= 1'b0; diff --git a/test_regress/t/t_clocker.v b/test_regress/t/t_clocker.v index 1385119b8..a29c1ff0b 100644 --- a/test_regress/t/t_clocker.v +++ b/test_regress/t/t_clocker.v @@ -16,9 +16,9 @@ module t (/*AUTOARG*/ res16 ); input clk; - output res; - output [7:0] res8; - output [15:0] res16; + output reg res; + output reg [7:0] res8; + output reg [15:0] res16; wire [7:0] clkSet; diff --git a/test_regress/t/t_dedupe_clk_gate.v b/test_regress/t/t_dedupe_clk_gate.v index fda3b8dc0..81cbc2af2 100644 --- a/test_regress/t/t_dedupe_clk_gate.v +++ b/test_regress/t/t_dedupe_clk_gate.v @@ -19,7 +19,7 @@ endmodule module flop_gated_latch(q,d,clk,en); input d, clk, en; - output q; + output reg q; wire gated_clock; clock_gate_latch clock_gate(gated_clock, clk, en); always @(posedge gated_clock) begin @@ -29,7 +29,7 @@ endmodule module flop_gated_flop(q,d,clk,en); input d, clk, en; - output q; + output reg q; wire gated_clock; clock_gate_flop clock_gate(gated_clock, clk, en); always @(posedge gated_clock) begin diff --git a/test_regress/t/t_dedupe_seq_logic.v b/test_regress/t/t_dedupe_seq_logic.v index 332214f14..82025b924 100644 --- a/test_regress/t/t_dedupe_seq_logic.v +++ b/test_regress/t/t_dedupe_seq_logic.v @@ -105,7 +105,7 @@ module rlr(sum,a,b,c,d,clk); endmodule module add(sum,x,y,clk); - output sum; + output reg sum; input x,y,clk; reg t1,t2; always @(posedge clk) begin @@ -114,7 +114,7 @@ module add(sum,x,y,clk); endmodule module add2(sum,x,y,clk); - output sum; + output reg sum; input x,y,clk; reg t1,t2; always @(posedge clk) begin diff --git a/test_regress/t/t_embed1_child.v b/test_regress/t/t_embed1_child.v index 84f118ae3..ff7749727 100644 --- a/test_regress/t/t_embed1_child.v +++ b/test_regress/t/t_embed1_child.v @@ -14,9 +14,9 @@ module t_embed1_child (/*AUTOARG*/ input bit_in; output bit_out; input [30:0] vec_in; - output [30:0] vec_out; + output logic [30:0] vec_out; input [123:0] wide_in; - output [123:0] wide_out; + output logic [123:0] wide_out; output did_init_out; input is_ref; diff --git a/test_regress/t/t_embed1_wrap.v b/test_regress/t/t_embed1_wrap.v index 9afca7bf9..da05a63dd 100644 --- a/test_regress/t/t_embed1_wrap.v +++ b/test_regress/t/t_embed1_wrap.v @@ -12,13 +12,13 @@ module t_embed1_wrap (/*AUTOARG*/ /*AUTOINOUTMODULE("t_embed1_child")*/ // Beginning of automatic in/out/inouts (from specific module) - output bit_out; - output [30:0] vec_out; - output [123:0] wide_out; - output did_init_out; + output bit bit_out; + output bit [30:0] vec_out; + output bit [123:0] wide_out; + output bit did_init_out; input clk; input bit_in; - input [30:0] vec_in; + input [30:0] vec_in; input [123:0] wide_in; input is_ref; // End of automatics diff --git a/test_regress/t/t_emit_memb_limit.pl b/test_regress/t/t_emit_memb_limit.pl index 9bffbbfba..39d551319 100755 --- a/test_regress/t/t_emit_memb_limit.pl +++ b/test_regress/t/t_emit_memb_limit.pl @@ -16,10 +16,10 @@ sub gen { my $fh = IO::File->new(">$filename"); $fh->print("// Generated by t_emit_memb_limit.pl\n"); - $fh->print("module t (i,clk,o);\n"); + $fh->print("module t (i, clk, o);\n"); $fh->print(" input clk;\n"); $fh->print(" input i;\n"); - $fh->print(" output o;\n"); + $fh->print(" output logic o;\n"); for (my $i=0; $i<($n+1); ++$i) { $fh->print(" logic r$i;\n"); } diff --git a/test_regress/t/t_extend_class.v b/test_regress/t/t_extend_class.v index fa3e3bcb4..25250d88b 100644 --- a/test_regress/t/t_extend_class.v +++ b/test_regress/t/t_extend_class.v @@ -38,7 +38,7 @@ module t_extend_class_v (/*AUTOARG*/ ); input [31:0] in; - output [31:0] out; + output logic [31:0] out; always @* begin // When "in" changes, call my method diff --git a/test_regress/t/t_func_unit.v b/test_regress/t/t_func_unit.v index 14d533f56..178d32480 100644 --- a/test_regress/t/t_func_unit.v +++ b/test_regress/t/t_func_unit.v @@ -3,15 +3,15 @@ // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Wilson Snyder. -task tsk(output fo); - assign fo = 1'b0; +task tsk(output tfo); + tfo = 1'b0; endtask module t (/*AUTOARG*/ // Outputs to ); - output to[2:0]; + output reg to[2:0]; integer i = 0; diff --git a/test_regress/t/t_mem_slot.v b/test_regress/t/t_mem_slot.v index bc35f2831..0811b9a29 100644 --- a/test_regress/t/t_mem_slot.v +++ b/test_regress/t/t_mem_slot.v @@ -12,7 +12,7 @@ module t_mem_slot (Clk, SlotIdx, BitToChange, BitVal, SlotToReturn, OutputVal); input BitToChange; input BitVal; input [1:0] SlotToReturn; - output [1:0] OutputVal; + output reg [1:0] OutputVal; reg [1:0] Array[2:0]; diff --git a/test_regress/t/t_order_multidriven.v b/test_regress/t/t_order_multidriven.v index d3202dfe6..ebe854786 100644 --- a/test_regress/t/t_order_multidriven.v +++ b/test_regress/t/t_order_multidriven.v @@ -162,13 +162,13 @@ module FooMemImpl( input a_wen, input [7:0] a_addr, input [7:0] a_wdata, - output [7:0] a_rdata, + output reg [7:0] a_rdata, input b_clk, input b_wen, input [7:0] b_addr, input [7:0] b_wdata, - output [7:0] b_rdata + output reg [7:0] b_rdata ); /* verilator lint_off MULTIDRIVEN */ diff --git a/test_regress/t/t_struct_anon.v b/test_regress/t/t_struct_anon.v index 2287a589c..cad5c4144 100644 --- a/test_regress/t/t_struct_anon.v +++ b/test_regress/t/t_struct_anon.v @@ -15,8 +15,8 @@ struct packed { } struct2; module t ( - output [63:0] s1, - output [63:0] s2 + output logic [63:0] s1, + output logic [63:0] s2 ); initial struct1 = 64'h123456789_abcdef0; always_comb s1 = struct1; diff --git a/test_regress/t/t_trace_fst.out b/test_regress/t/t_trace_fst.out index 8661a0205..d6453e931 100644 --- a/test_regress/t/t_trace_fst.out +++ b/test_regress/t/t_trace_fst.out @@ -1,5 +1,5 @@ $date - Sun Oct 21 21:55:42 2018 + Tue Nov 5 20:18:53 2019 $end $version @@ -30,23 +30,23 @@ $var parameter 32 . fst_parameter $end $var parameter 32 / fst_lparam $end $var supply0 1 0 fst_supply0 $end $var supply1 1 1 fst_supply1 $end -$var tri0 1 0 fst_tri0 $end -$var tri1 1 1 fst_tri1 $end -$var tri 1 2 fst_tri $end -$var wire 1 3 fst_wire $end +$var tri0 1 2 fst_tri0 $end +$var tri1 1 3 fst_tri1 $end +$var tri 1 4 fst_tri $end +$var wire 1 5 fst_wire $end $scope module test $end $var wire 1 ! clk $end $var wire 1 $ rstn $end $var wire 5 " state $end -$var logic 5 4 state_w $end -$var logic 5 5 state_array(0) $end -$var logic 5 6 state_array(1) $end -$var logic 5 7 state_array(2) $end +$var logic 5 6 state_w $end +$var logic 5 7 state_array(0) $end +$var logic 5 8 state_array(1) $end +$var logic 5 9 state_array(2) $end $scope module unnamedblk2 $end -$var int 32 8 i $end +$var int 32 : i $end $upscope $end $scope module unnamedblk1 $end -$var int 32 9 i $end +$var int 32 ; i $end $upscope $end $upscope $end $upscope $end @@ -71,20 +71,22 @@ b00000000000000000000000111001000 / 00 11 02 -03 -b00000 4 -b00000 5 +13 +04 +05 b00000 6 b00000 7 -b00000000000000000000000000000000 8 -b00000000000000000000000000000000 9 +b00000 8 +b00000 9 +b00000000000000000000000000000000 : +b00000000000000000000000000000000 ; #10 -b00000000000000000000000000000011 9 -b00000000000000000000000000000000 8 +b00000000000000000000000000000011 ; +b00000000000000000000000000000000 : +b00001 9 +b00001 8 b00001 7 -b00001 6 -b00001 5 -b10100 4 +b10100 6 0$ b00000000000000000000000000000001 # b00001 " @@ -97,24 +99,24 @@ b00001 " 1! b00000000000000000000000000000010 # 0$ -b10100 4 -b00001 5 -b00001 6 +b10100 6 b00001 7 -b00000000000000000000000000000000 8 -b00000000000000000000000000000011 9 +b00001 8 +b00001 9 +b00000000000000000000000000000000 : +b00000000000000000000000000000011 ; #25 0! b00001 " #30 b00001 " 1! -b00000000000000000000000000000011 9 -b00000000000000000000000000000000 8 +b00000000000000000000000000000011 ; +b00000000000000000000000000000000 : +b00001 9 +b00001 8 b00001 7 -b00001 6 -b00001 5 -b10100 4 +b10100 6 0$ b00000000000000000000000000000011 # #35 @@ -125,24 +127,24 @@ b00001 " 1! b00000000000000000000000000000100 # 0$ -b10100 4 -b00001 5 -b00001 6 +b10100 6 b00001 7 -b00000000000000000000000000000000 8 -b00000000000000000000000000000011 9 +b00001 8 +b00001 9 +b00000000000000000000000000000000 : +b00000000000000000000000000000011 ; #45 0! b00001 " #50 b00001 " 1! -b00000000000000000000000000000011 9 -b00000000000000000000000000000000 8 +b00000000000000000000000000000011 ; +b00000000000000000000000000000000 : +b00001 9 +b00001 8 b00001 7 -b00001 6 -b00001 5 -b10100 4 +b10100 6 0$ b00000000000000000000000000000101 # #55 @@ -153,24 +155,24 @@ b00001 " 1! b00000000000000000000000000000110 # 0$ -b10100 4 -b00001 5 -b00001 6 +b10100 6 b00001 7 -b00000000000000000000000000000000 8 -b00000000000000000000000000000011 9 +b00001 8 +b00001 9 +b00000000000000000000000000000000 : +b00000000000000000000000000000011 ; #65 0! b00001 " #70 b00001 " 1! -b00000000000000000000000000000011 9 -b00000000000000000000000000000000 8 +b00000000000000000000000000000011 ; +b00000000000000000000000000000000 : +b00001 9 +b00001 8 b00001 7 -b00001 6 -b00001 5 -b10100 4 +b10100 6 0$ b00000000000000000000000000000111 # #75 @@ -181,24 +183,24 @@ b00001 " 1! b00000000000000000000000000001000 # 0$ -b10100 4 -b00001 5 -b00001 6 +b10100 6 b00001 7 -b00000000000000000000000000000000 8 -b00000000000000000000000000000011 9 +b00001 8 +b00001 9 +b00000000000000000000000000000000 : +b00000000000000000000000000000011 ; #85 0! b00001 " #90 b00001 " 1! -b00000000000000000000000000000011 9 -b00000000000000000000000000000000 8 +b00000000000000000000000000000011 ; +b00000000000000000000000000000000 : +b00001 9 +b00001 8 b00001 7 -b00001 6 -b00001 5 -b10100 4 +b10100 6 0$ b00000000000000000000000000001001 # #95 @@ -209,24 +211,24 @@ b00001 " 1! b00000000000000000000000000001010 # 0$ -b10100 4 -b00001 5 -b00001 6 +b10100 6 b00001 7 -b00000000000000000000000000000000 8 -b00000000000000000000000000000011 9 +b00001 8 +b00001 9 +b00000000000000000000000000000000 : +b00000000000000000000000000000011 ; #105 0! b00001 " #110 b00001 " 1! -b00000000000000000000000000000011 9 -b00000000000000000000000000000000 8 +b00000000000000000000000000000011 ; +b00000000000000000000000000000000 : +b00001 9 +b00001 8 b00001 7 -b00001 6 -b00001 5 -b10100 4 +b10100 6 1$ b00000000000000000000000000001011 # #115 @@ -237,24 +239,24 @@ b00001 " 1! b00000000000000000000000000001100 # 1$ -b01010 4 -b00001 5 -b00001 6 -b10100 7 -b00000000000000000000000000000010 8 -b00000000000000000000000000000011 9 +b01010 6 +b00001 7 +b00001 8 +b10100 9 +b00000000000000000000000000000010 : +b00000000000000000000000000000011 ; #125 0! b00001 " #130 b00001 " 1! -b00000000000000000000000000000011 9 -b00000000000000000000000000000010 8 -b01010 7 -b10100 6 -b00001 5 -b00101 4 +b00000000000000000000000000000011 ; +b00000000000000000000000000000010 : +b01010 9 +b10100 8 +b00001 7 +b00101 6 1$ b00000000000000000000000000001101 # #135 @@ -265,24 +267,24 @@ b10100 " 1! b00000000000000000000000000001110 # 1$ -b10110 4 -b10100 5 -b01010 6 -b00101 7 -b00000000000000000000000000000010 8 -b00000000000000000000000000000011 9 +b10110 6 +b10100 7 +b01010 8 +b00101 9 +b00000000000000000000000000000010 : +b00000000000000000000000000000011 ; #145 0! b10100 " #150 b01010 " 1! -b00000000000000000000000000000011 9 -b00000000000000000000000000000010 8 -b10110 7 -b00101 6 -b01010 5 -b01011 4 +b00000000000000000000000000000011 ; +b00000000000000000000000000000010 : +b10110 9 +b00101 8 +b01010 7 +b01011 6 1$ b00000000000000000000000000001111 # #155 @@ -293,24 +295,24 @@ b00101 " 1! b00000000000000000000000000010000 # 1$ -b10001 4 -b00101 5 -b10110 6 -b01011 7 -b00000000000000000000000000000010 8 -b00000000000000000000000000000011 9 +b10001 6 +b00101 7 +b10110 8 +b01011 9 +b00000000000000000000000000000010 : +b00000000000000000000000000000011 ; #165 0! b00101 " #170 b10110 " 1! -b00000000000000000000000000000011 9 -b00000000000000000000000000000010 8 -b10001 7 -b01011 6 -b10110 5 -b11100 4 +b00000000000000000000000000000011 ; +b00000000000000000000000000000010 : +b10001 9 +b01011 8 +b10110 7 +b11100 6 1$ b00000000000000000000000000010001 # #175 @@ -321,24 +323,24 @@ b01011 " 1! b00000000000000000000000000010010 # 1$ -b01110 4 -b01011 5 -b10001 6 -b11100 7 -b00000000000000000000000000000010 8 -b00000000000000000000000000000011 9 +b01110 6 +b01011 7 +b10001 8 +b11100 9 +b00000000000000000000000000000010 : +b00000000000000000000000000000011 ; #185 0! b01011 " #190 b10001 " 1! -b00000000000000000000000000000011 9 -b00000000000000000000000000000010 8 -b01110 7 -b11100 6 -b10001 5 -b00111 4 +b00000000000000000000000000000011 ; +b00000000000000000000000000000010 : +b01110 9 +b11100 8 +b10001 7 +b00111 6 1$ b00000000000000000000000000010011 # #195 @@ -349,24 +351,24 @@ b11100 " 1! b00000000000000000000000000010100 # 1$ -b10111 4 -b11100 5 -b01110 6 -b00111 7 -b00000000000000000000000000000010 8 -b00000000000000000000000000000011 9 +b10111 6 +b11100 7 +b01110 8 +b00111 9 +b00000000000000000000000000000010 : +b00000000000000000000000000000011 ; #205 0! b11100 " #210 b01110 " 1! -b00000000000000000000000000000011 9 -b00000000000000000000000000000010 8 -b10111 7 -b00111 6 -b01110 5 -b11111 4 +b00000000000000000000000000000011 ; +b00000000000000000000000000000010 : +b10111 9 +b00111 8 +b01110 7 +b11111 6 1$ b00000000000000000000000000010101 # #215 @@ -377,24 +379,24 @@ b00111 " 1! b00000000000000000000000000010110 # 1$ -b11011 4 -b00111 5 -b10111 6 -b11111 7 -b00000000000000000000000000000010 8 -b00000000000000000000000000000011 9 +b11011 6 +b00111 7 +b10111 8 +b11111 9 +b00000000000000000000000000000010 : +b00000000000000000000000000000011 ; #225 0! b00111 " #230 b10111 " 1! -b00000000000000000000000000000011 9 -b00000000000000000000000000000010 8 -b11011 7 -b11111 6 -b10111 5 -b11001 4 +b00000000000000000000000000000011 ; +b00000000000000000000000000000010 : +b11011 9 +b11111 8 +b10111 7 +b11001 6 1$ b00000000000000000000000000010111 # #235 @@ -405,24 +407,24 @@ b11111 " 1! b00000000000000000000000000011000 # 1$ -b11000 4 -b11111 5 -b11011 6 -b11001 7 -b00000000000000000000000000000010 8 -b00000000000000000000000000000011 9 +b11000 6 +b11111 7 +b11011 8 +b11001 9 +b00000000000000000000000000000010 : +b00000000000000000000000000000011 ; #245 0! b11111 " #250 b11011 " 1! -b00000000000000000000000000000011 9 -b00000000000000000000000000000010 8 -b11000 7 -b11001 6 -b11011 5 -b01100 4 +b00000000000000000000000000000011 ; +b00000000000000000000000000000010 : +b11000 9 +b11001 8 +b11011 7 +b01100 6 1$ b00000000000000000000000000011001 # #255 @@ -433,24 +435,24 @@ b11001 " 1! b00000000000000000000000000011010 # 1$ -b00110 4 -b11001 5 -b11000 6 -b01100 7 -b00000000000000000000000000000010 8 -b00000000000000000000000000000011 9 +b00110 6 +b11001 7 +b11000 8 +b01100 9 +b00000000000000000000000000000010 : +b00000000000000000000000000000011 ; #265 0! b11001 " #270 b11000 " 1! -b00000000000000000000000000000011 9 -b00000000000000000000000000000010 8 -b00110 7 -b01100 6 -b11000 5 -b00011 4 +b00000000000000000000000000000011 ; +b00000000000000000000000000000010 : +b00110 9 +b01100 8 +b11000 7 +b00011 6 1$ b00000000000000000000000000011011 # #275 @@ -461,24 +463,24 @@ b01100 " 1! b00000000000000000000000000011100 # 1$ -b10101 4 -b01100 5 -b00110 6 -b00011 7 -b00000000000000000000000000000010 8 -b00000000000000000000000000000011 9 +b10101 6 +b01100 7 +b00110 8 +b00011 9 +b00000000000000000000000000000010 : +b00000000000000000000000000000011 ; #285 0! b01100 " #290 b00110 " 1! -b00000000000000000000000000000011 9 -b00000000000000000000000000000010 8 -b10101 7 -b00011 6 -b00110 5 -b11110 4 +b00000000000000000000000000000011 ; +b00000000000000000000000000000010 : +b10101 9 +b00011 8 +b00110 7 +b11110 6 1$ b00000000000000000000000000011101 # #295 @@ -489,24 +491,24 @@ b00011 " 1! b00000000000000000000000000011110 # 1$ -b01111 4 -b00011 5 -b10101 6 -b11110 7 -b00000000000000000000000000000010 8 -b00000000000000000000000000000011 9 +b01111 6 +b00011 7 +b10101 8 +b11110 9 +b00000000000000000000000000000010 : +b00000000000000000000000000000011 ; #305 0! b00011 " #310 b10101 " 1! -b00000000000000000000000000000011 9 -b00000000000000000000000000000010 8 -b01111 7 -b11110 6 -b10101 5 -b10011 4 +b00000000000000000000000000000011 ; +b00000000000000000000000000000010 : +b01111 9 +b11110 8 +b10101 7 +b10011 6 1$ b00000000000000000000000000011111 # #315 @@ -517,24 +519,24 @@ b11110 " 1! b00000000000000000000000000100000 # 1$ -b11101 4 -b11110 5 -b01111 6 -b10011 7 -b00000000000000000000000000000010 8 -b00000000000000000000000000000011 9 +b11101 6 +b11110 7 +b01111 8 +b10011 9 +b00000000000000000000000000000010 : +b00000000000000000000000000000011 ; #325 0! b11110 " #330 b01111 " 1! -b00000000000000000000000000000011 9 -b00000000000000000000000000000010 8 -b11101 7 -b10011 6 -b01111 5 -b11010 4 +b00000000000000000000000000000011 ; +b00000000000000000000000000000010 : +b11101 9 +b10011 8 +b01111 7 +b11010 6 1$ b00000000000000000000000000100001 # #335 @@ -545,24 +547,24 @@ b10011 " 1! b00000000000000000000000000100010 # 1$ -b01101 4 -b10011 5 -b11101 6 -b11010 7 -b00000000000000000000000000000010 8 -b00000000000000000000000000000011 9 +b01101 6 +b10011 7 +b11101 8 +b11010 9 +b00000000000000000000000000000010 : +b00000000000000000000000000000011 ; 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#705 0! b01001 " #710 b10000 " 1! -b00000000000000000000000000000011 9 -b00000000000000000000000000000010 8 -b00100 7 -b01000 6 -b10000 5 -b00010 4 +b00000000000000000000000000000011 ; +b00000000000000000000000000000010 : +b00100 9 +b01000 8 +b10000 7 +b00010 6 1$ b00000000000000000000000001000111 # #715 @@ -1077,24 +1079,24 @@ b01000 " 1! b00000000000000000000000001001000 # 1$ -b00001 4 -b01000 5 -b00100 6 -b00010 7 -b00000000000000000000000000000010 8 -b00000000000000000000000000000011 9 +b00001 6 +b01000 7 +b00100 8 +b00010 9 +b00000000000000000000000000000010 : +b00000000000000000000000000000011 ; #725 0! b01000 " #730 b00100 " 1! -b00000000000000000000000000000011 9 -b00000000000000000000000000000010 8 -b00001 7 -b00010 6 -b00100 5 -b10100 4 +b00000000000000000000000000000011 ; +b00000000000000000000000000000010 : +b00001 9 +b00010 8 +b00100 7 +b10100 6 1$ b00000000000000000000000001001001 # #735 @@ -1105,24 +1107,24 @@ b00010 " 1! b00000000000000000000000001001010 # 1$ -b01010 4 -b00010 5 -b00001 6 -b10100 7 -b00000000000000000000000000000010 8 -b00000000000000000000000000000011 9 +b01010 6 +b00010 7 +b00001 8 +b10100 9 +b00000000000000000000000000000010 : +b00000000000000000000000000000011 ; #745 0! b00010 " #750 b00001 " 1! -b00000000000000000000000000000011 9 -b00000000000000000000000000000010 8 -b01010 7 -b10100 6 -b00001 5 -b00101 4 +b00000000000000000000000000000011 ; +b00000000000000000000000000000010 : +b01010 9 +b10100 8 +b00001 7 +b00101 6 1$ b00000000000000000000000001001011 # #755 @@ -1133,24 +1135,24 @@ b10100 " 1! b00000000000000000000000001001100 # 1$ -b10110 4 -b10100 5 -b01010 6 -b00101 7 -b00000000000000000000000000000010 8 -b00000000000000000000000000000011 9 +b10110 6 +b10100 7 +b01010 8 +b00101 9 +b00000000000000000000000000000010 : +b00000000000000000000000000000011 ; #765 0! b10100 " #770 b01010 " 1! -b00000000000000000000000000000011 9 -b00000000000000000000000000000010 8 -b10110 7 -b00101 6 -b01010 5 -b01011 4 +b00000000000000000000000000000011 ; +b00000000000000000000000000000010 : +b10110 9 +b00101 8 +b01010 7 +b01011 6 1$ b00000000000000000000000001001101 # #775 @@ -1161,24 +1163,24 @@ b00101 " 1! b00000000000000000000000001001110 # 1$ -b10001 4 -b00101 5 -b10110 6 -b01011 7 -b00000000000000000000000000000010 8 -b00000000000000000000000000000011 9 +b10001 6 +b00101 7 +b10110 8 +b01011 9 +b00000000000000000000000000000010 : +b00000000000000000000000000000011 ; #785 0! b00101 " #790 b10110 " 1! -b00000000000000000000000000000011 9 -b00000000000000000000000000000010 8 -b10001 7 -b01011 6 -b10110 5 -b11100 4 +b00000000000000000000000000000011 ; +b00000000000000000000000000000010 : +b10001 9 +b01011 8 +b10110 7 +b11100 6 1$ b00000000000000000000000001001111 # #795 @@ -1189,24 +1191,24 @@ b01011 " 1! b00000000000000000000000001010000 # 1$ -b01110 4 -b01011 5 -b10001 6 -b11100 7 -b00000000000000000000000000000010 8 -b00000000000000000000000000000011 9 +b01110 6 +b01011 7 +b10001 8 +b11100 9 +b00000000000000000000000000000010 : +b00000000000000000000000000000011 ; #805 0! b01011 " #810 b10001 " 1! -b00000000000000000000000000000011 9 -b00000000000000000000000000000010 8 -b01110 7 -b11100 6 -b10001 5 -b00111 4 +b00000000000000000000000000000011 ; +b00000000000000000000000000000010 : +b01110 9 +b11100 8 +b10001 7 +b00111 6 1$ b00000000000000000000000001010001 # #815 @@ -1217,24 +1219,24 @@ b11100 " 1! b00000000000000000000000001010010 # 1$ -b10111 4 -b11100 5 -b01110 6 -b00111 7 -b00000000000000000000000000000010 8 -b00000000000000000000000000000011 9 +b10111 6 +b11100 7 +b01110 8 +b00111 9 +b00000000000000000000000000000010 : +b00000000000000000000000000000011 ; #825 0! b11100 " #830 b01110 " 1! -b00000000000000000000000000000011 9 -b00000000000000000000000000000010 8 -b10111 7 -b00111 6 -b01110 5 -b11111 4 +b00000000000000000000000000000011 ; +b00000000000000000000000000000010 : +b10111 9 +b00111 8 +b01110 7 +b11111 6 1$ b00000000000000000000000001010011 # #835 @@ -1245,24 +1247,24 @@ b00111 " 1! b00000000000000000000000001010100 # 1$ -b11011 4 -b00111 5 -b10111 6 -b11111 7 -b00000000000000000000000000000010 8 -b00000000000000000000000000000011 9 +b11011 6 +b00111 7 +b10111 8 +b11111 9 +b00000000000000000000000000000010 : +b00000000000000000000000000000011 ; #845 0! b00111 " #850 b10111 " 1! -b00000000000000000000000000000011 9 -b00000000000000000000000000000010 8 -b11011 7 -b11111 6 -b10111 5 -b11001 4 +b00000000000000000000000000000011 ; +b00000000000000000000000000000010 : +b11011 9 +b11111 8 +b10111 7 +b11001 6 1$ b00000000000000000000000001010101 # #855 @@ -1273,24 +1275,24 @@ b11111 " 1! b00000000000000000000000001010110 # 1$ -b11000 4 -b11111 5 -b11011 6 -b11001 7 -b00000000000000000000000000000010 8 -b00000000000000000000000000000011 9 +b11000 6 +b11111 7 +b11011 8 +b11001 9 +b00000000000000000000000000000010 : +b00000000000000000000000000000011 ; #865 0! b11111 " #870 b11011 " 1! -b00000000000000000000000000000011 9 -b00000000000000000000000000000010 8 -b11000 7 -b11001 6 -b11011 5 -b01100 4 +b00000000000000000000000000000011 ; +b00000000000000000000000000000010 : +b11000 9 +b11001 8 +b11011 7 +b01100 6 1$ b00000000000000000000000001010111 # #875 @@ -1301,24 +1303,24 @@ b11001 " 1! b00000000000000000000000001011000 # 1$ -b00110 4 -b11001 5 -b11000 6 -b01100 7 -b00000000000000000000000000000010 8 -b00000000000000000000000000000011 9 +b00110 6 +b11001 7 +b11000 8 +b01100 9 +b00000000000000000000000000000010 : +b00000000000000000000000000000011 ; #885 0! b11001 " #890 b11000 " 1! -b00000000000000000000000000000011 9 -b00000000000000000000000000000010 8 -b00110 7 -b01100 6 -b11000 5 -b00011 4 +b00000000000000000000000000000011 ; +b00000000000000000000000000000010 : +b00110 9 +b01100 8 +b11000 7 +b00011 6 1$ b00000000000000000000000001011001 # #895 @@ -1329,24 +1331,24 @@ b01100 " 1! b00000000000000000000000001011010 # 1$ -b10101 4 -b01100 5 -b00110 6 -b00011 7 -b00000000000000000000000000000010 8 -b00000000000000000000000000000011 9 +b10101 6 +b01100 7 +b00110 8 +b00011 9 +b00000000000000000000000000000010 : +b00000000000000000000000000000011 ; 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#945 0! b11110 " #950 b01111 " 1! -b00000000000000000000000000000011 9 -b00000000000000000000000000000010 8 -b11101 7 -b10011 6 -b01111 5 -b11010 4 +b00000000000000000000000000000011 ; +b00000000000000000000000000000010 : +b11101 9 +b10011 8 +b01111 7 +b11010 6 1$ b00000000000000000000000001011111 # #955 @@ -1413,24 +1415,24 @@ b10011 " 1! b00000000000000000000000001100000 # 1$ -b01101 4 -b10011 5 -b11101 6 -b11010 7 -b00000000000000000000000000000010 8 -b00000000000000000000000000000011 9 +b01101 6 +b10011 7 +b11101 8 +b11010 9 +b00000000000000000000000000000010 : +b00000000000000000000000000000011 ; #965 0! b10011 " #970 b11101 " 1! -b00000000000000000000000000000011 9 -b00000000000000000000000000000010 8 -b01101 7 -b11010 6 -b11101 5 -b10010 4 +b00000000000000000000000000000011 ; +b00000000000000000000000000000010 : +b01101 9 +b11010 8 +b11101 7 +b10010 6 1$ b00000000000000000000000001100001 # #975 @@ -1441,24 +1443,24 @@ b11010 " 1! b00000000000000000000000001100010 # 1$ -b01001 4 -b11010 5 -b01101 6 -b10010 7 -b00000000000000000000000000000010 8 -b00000000000000000000000000000011 9 +b01001 6 +b11010 7 +b01101 8 +b10010 9 +b00000000000000000000000000000010 : +b00000000000000000000000000000011 ; #985 0! b11010 " #990 b01101 " 1! -b00000000000000000000000000000011 9 -b00000000000000000000000000000010 8 -b01001 7 -b10010 6 -b01101 5 -b10000 4 +b00000000000000000000000000000011 ; +b00000000000000000000000000000010 : +b01001 9 +b10010 8 +b01101 7 +b10000 6 1$ b00000000000000000000000001100011 # #995 @@ -1469,9 +1471,9 @@ b10010 " 1! b00000000000000000000000001100100 # 1$ -b01000 4 -b10010 5 -b01001 6 -b10000 7 -b00000000000000000000000000000010 8 -b00000000000000000000000000000011 9 +b01000 6 +b10010 7 +b01001 8 +b10000 9 +b00000000000000000000000000000010 : +b00000000000000000000000000000011 ; diff --git a/test_regress/t/t_var_dup_bad.out b/test_regress/t/t_var_dup_bad.out index 7ecf933e6..4ef6a902d 100644 --- a/test_regress/t/t_var_dup_bad.out +++ b/test_regress/t/t_var_dup_bad.out @@ -47,6 +47,7 @@ output bad_reout_port ^~~~~~~~~~~~~~ %Error: t/t_var_dup_bad.v:72: Duplicate declaration of signal: 'bad_rewire' + : ... note: ANSI ports must have type declared with the I/O (IEEE 2017 23.2.2.2) wire bad_rewire; ^~~~~~~~~~ t/t_var_dup_bad.v:69: ... Location of original declaration diff --git a/test_regress/t/t_var_pinsizes.v b/test_regress/t/t_var_pinsizes.v index 89aa944ff..1ed04a606 100644 --- a/test_regress/t/t_var_pinsizes.v +++ b/test_regress/t/t_var_pinsizes.v @@ -26,22 +26,22 @@ module t (/*AUTOARG*/ input i1a2 [1:0]; input [93:0] i94a3 [2:0]; - output o1; - output [7:0] o8; - output [15:0] o16; - output [31:0] o32; - output [63:0] o64; - output [64:0] o65; - output [127:0] o128; - output [512:0] o513; - output o1a2 [1:0]; - output [93:0] o94a3 [2:0]; + output logic o1; + output logic [7:0] o8; + output logic [15:0] o16; + output logic [31:0] o32; + output logic [63:0] o64; + output logic [64:0] o65; + output logic [127:0] o128; + output logic [512:0] o513; + output logic o1a2 [1:0]; + output logic [93:0] o94a3 [2:0]; input [0:0] ibv1 /*verilator sc_bv*/; input [15:0] ibv16 /*verilator sc_bv*/; - output [0:0] obv1 /*verilator sc_bv*/; - output [15:0] obv16 /*verilator sc_bv*/; + output logic [0:0] obv1 /*verilator sc_bv*/; + output logic [15:0] obv16 /*verilator sc_bv*/; always @ (posedge clk) begin o1 <= i1; diff --git a/test_regress/t/t_wire_beh1364_bad.out b/test_regress/t/t_wire_beh1364_bad.out new file mode 100644 index 000000000..6964a527b --- /dev/null +++ b/test_regress/t/t_wire_beh1364_bad.out @@ -0,0 +1,13 @@ +%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:22: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w' + : ... In instance t + w = '0; + ^ +%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:23: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'o' + : ... In instance t + o = '0; + ^ +%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:24: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'oa' + : ... In instance t + oa = '0; + ^~ +%Error: Exiting due to diff --git a/test_regress/t/t_wire_beh_bad.pl b/test_regress/t/t_wire_beh1364_bad.pl similarity index 100% rename from test_regress/t/t_wire_beh_bad.pl rename to test_regress/t/t_wire_beh1364_bad.pl diff --git a/test_regress/t/t_wire_beh1364_bad.v b/test_regress/t/t_wire_beh1364_bad.v new file mode 100644 index 000000000..daa6d89de --- /dev/null +++ b/test_regress/t/t_wire_beh1364_bad.v @@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + o, oa, ro, roa + ); + + wire w; + reg r; + output o; + output [1:0] oa; + output reg ro; + output reg [1:0] roa; + //1800 only: + //output var vo; + //output var [1:0] voa; + + initial begin + w = '0; // Error + o = '0; // Error + oa = '0; // Error + r = '0; // Not an error + ro = '0; // Not an error + roa = '0; // Not an error + //vo = '0; // Not an error + //voa = '0; // Not an error + end + +endmodule diff --git a/test_regress/t/t_wire_beh1800_bad.out b/test_regress/t/t_wire_beh1800_bad.out new file mode 100644 index 000000000..b3354704a --- /dev/null +++ b/test_regress/t/t_wire_beh1800_bad.out @@ -0,0 +1,13 @@ +%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:22: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w' + : ... In instance t + w = '0; + ^ +%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:23: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'o' + : ... In instance t + o = '0; + ^ +%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:24: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'oa' + : ... In instance t + oa = '0; + ^~ +%Error: Exiting due to diff --git a/test_regress/t/t_wire_beh1800_bad.pl b/test_regress/t/t_wire_beh1800_bad.pl new file mode 100755 index 000000000..8c9b1887a --- /dev/null +++ b/test_regress/t/t_wire_beh1800_bad.pl @@ -0,0 +1,19 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +scenarios(vlt => 1); + +lint( + verilator_flags2 => ["--lint-only --language 1800-2017"], + fails => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_wire_beh1800_bad.v b/test_regress/t/t_wire_beh1800_bad.v new file mode 100644 index 000000000..12b814840 --- /dev/null +++ b/test_regress/t/t_wire_beh1800_bad.v @@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + o, oa, ro, roa, vo, voa + ); + + wire w; + reg r; + output o; + output [1:0] oa; + output reg ro; + output reg [1:0] roa; + // 1800 only + output var vo; + output var [1:0] voa; + + initial begin + w = '0; // Error + o = '0; // Error + oa = '0; // Error + r = '0; // Not an error + ro = '0; // Not an error + roa = '0; // Not an error + vo = '0; // Not an error + voa = '0; // Not an error + end + +endmodule diff --git a/test_regress/t/t_wire_beh_bad.out b/test_regress/t/t_wire_beh_bad.out deleted file mode 100644 index 81fc7c475..000000000 --- a/test_regress/t/t_wire_beh_bad.out +++ /dev/null @@ -1,9 +0,0 @@ -%Error-CONTASSREG: t/t_wire_beh_bad.v:11: Continuous assignment to reg, perhaps intended wire (IEEE 2005 6.1; Verilog only, legal in SV): 'r' - : ... In instance t - assign r = 1'b1; - ^ -%Error-PROCASSWIRE: t/t_wire_beh_bad.v:12: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w' - : ... In instance t - always @ (r) w = 1'b0; - ^ -%Error: Exiting due to diff --git a/test_regress/t/t_wire_beh_bad.v b/test_regress/t/t_wire_beh_bad.v deleted file mode 100644 index b6478afe5..000000000 --- a/test_regress/t/t_wire_beh_bad.v +++ /dev/null @@ -1,14 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2018 by Wilson Snyder. - -module t (/*AUTOARG*/); - - wire w; - reg r; - - assign r = 1'b1; - always @ (r) w = 1'b0; - -endmodule diff --git a/test_regress/t/t_wire_behp1364_bad.out b/test_regress/t/t_wire_behp1364_bad.out new file mode 100644 index 000000000..144c960d0 --- /dev/null +++ b/test_regress/t/t_wire_behp1364_bad.out @@ -0,0 +1,13 @@ +%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:20: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w' + : ... In instance t + w = '0; + ^ +%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:21: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'o' + : ... In instance t + o = '0; + ^ +%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:22: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'oa' + : ... In instance t + oa = '0; + ^~ +%Error: Exiting due to diff --git a/test_regress/t/t_wire_behp1364_bad.pl b/test_regress/t/t_wire_behp1364_bad.pl new file mode 100755 index 000000000..fa3fa6b10 --- /dev/null +++ b/test_regress/t/t_wire_behp1364_bad.pl @@ -0,0 +1,19 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +scenarios(vlt => 1); + +lint( + verilator_flags2 => ["--lint-only --language 1364-2001"], + fails => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_wire_behp1364_bad.v b/test_regress/t/t_wire_behp1364_bad.v new file mode 100644 index 000000000..0af6c1eb0 --- /dev/null +++ b/test_regress/t/t_wire_behp1364_bad.v @@ -0,0 +1,30 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Wilson Snyder. + +module t ( + output o, + output [1:0] oa, + output reg ro, + output reg [1:0] roa + //1800 only: + //output var vo; + //output var [1:0] voa; + ); + + wire w; + reg r; + + initial begin + w = '0; // Error + o = '0; // Error + oa = '0; // Error + r = '0; // Not an error + ro = '0; // Not an error + roa = '0; // Not an error + //vo = '0; // Not an error + //voa = '0; // Not an error + end + +endmodule diff --git a/test_regress/t/t_wire_behp1800_bad.out b/test_regress/t/t_wire_behp1800_bad.out new file mode 100644 index 000000000..21d612cfa --- /dev/null +++ b/test_regress/t/t_wire_behp1800_bad.out @@ -0,0 +1,13 @@ +%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:20: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w' + : ... In instance t + w = '0; + ^ +%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:21: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'o' + : ... In instance t + o = '0; + ^ +%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:22: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'oa' + : ... In instance t + oa = '0; + ^~ +%Error: Exiting due to diff --git a/test_regress/t/t_wire_behp1800_bad.pl b/test_regress/t/t_wire_behp1800_bad.pl new file mode 100755 index 000000000..8c9b1887a --- /dev/null +++ b/test_regress/t/t_wire_behp1800_bad.pl @@ -0,0 +1,19 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +scenarios(vlt => 1); + +lint( + verilator_flags2 => ["--lint-only --language 1800-2017"], + fails => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_wire_behp1800_bad.v b/test_regress/t/t_wire_behp1800_bad.v new file mode 100644 index 000000000..773d0a1b9 --- /dev/null +++ b/test_regress/t/t_wire_behp1800_bad.v @@ -0,0 +1,30 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Wilson Snyder. + +module t ( + output o, + output [1:0] oa, + output reg ro, + output reg [1:0] roa, + // 1800 only + output var vo, + output var [1:0] voa + ); + + wire w; + reg r; + + initial begin + w = '0; // Error + o = '0; // Error + oa = '0; // Error + r = '0; // Not an error + ro = '0; // Not an error + roa = '0; // Not an error + vo = '0; // Not an error + voa = '0; // Not an error + end + +endmodule