diff --git a/src/V3EmitCFunc.h b/src/V3EmitCFunc.h
index dcee1eabe..389b5d012 100644
--- a/src/V3EmitCFunc.h
+++ b/src/V3EmitCFunc.h
@@ -1214,9 +1214,8 @@ public:
         puts(")");
     }
     void visit(AstNewCopy* nodep) override {
-        putns(nodep, "VL_NEW(" + prefixNameProtect(nodep->dtypep()) + ", "
-                         + optionalProcArg(nodep->dtypep()));
-        puts("*");  // i.e. make into a reference
+        putns(nodep, "VL_NEW(" + prefixNameProtect(nodep->dtypep()));
+        puts(", *");  // i.e. make into a reference
         iterateAndNextConstNull(nodep->rhsp());
         puts(")");
     }
diff --git a/test_regress/t/t_process_copy_constr.py b/test_regress/t/t_process_copy_constr.py
new file mode 100755
index 000000000..34b0247e9
--- /dev/null
+++ b/test_regress/t/t_process_copy_constr.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_flags2=["--timing"])
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_process_copy_constr.v b/test_regress/t/t_process_copy_constr.v
new file mode 100644
index 000000000..13f57775e
--- /dev/null
+++ b/test_regress/t/t_process_copy_constr.v
@@ -0,0 +1,25 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2024 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+class Cls;
+   int x = 1;
+   function new();
+      int p = process::self();
+   endfunction
+endclass
+
+module t (/*AUTOARG*/
+   );
+   initial begin
+      Cls c, d;
+      c = new;
+      c.x = 2;
+      d = new c;
+      if (d.x != 2) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule