diff --git a/Changes b/Changes
index 6bba79b79..e41bc37bd 100644
--- a/Changes
+++ b/Changes
@@ -28,6 +28,7 @@ Verilator 5.015 devel
 * Fix coroutine handle movement during queue manipulation (#4431). [Aleksander Kiryk, Antmicro Ltd]
 * Fix nested assignments on the LHS (#4435). [Ryszard Rozak, Antmicro Ltd]
 * Fix false MULTITOP on bound interfaces (#4438). [Alex Solomatnikov]
+* Fix internal error on real conversion (#4447). [vdhotre-ventana]
 
 
 Verilator 5.014 2023-08-06
diff --git a/src/V3Number.cpp b/src/V3Number.cpp
index c44c6e17c..38e7de3a2 100644
--- a/src/V3Number.cpp
+++ b/src/V3Number.cpp
@@ -511,6 +511,7 @@ string V3Number::ascii(bool prefixed, bool cleanVerilog) const VL_MT_STABLE {
             out << "%E-bad-width-double";  // LCOV_EXCL_LINE
         } else {
             out << toDouble();
+            if (toDouble() == floor(toDouble())) out << ".0";
         }
         return out.str();
     } else if (isString()) {
@@ -2217,8 +2218,9 @@ V3Number& V3Number::opAssignNonXZ(const V3Number& lhs, bool ignoreXZ) {
         } else if (VL_UNLIKELY(lhs.isString())) {
             // Non-compatible types, see also opAToN()
             setZero();
+        } else if (lhs.isDouble()) {
+            setDouble(lhs.toDouble());
         } else {
-            // Also handles double as is just bits
             for (int bit = 0; bit < this->width(); bit++) {
                 setBit(bit, ignoreXZ ? lhs.bitIs1(bit) : lhs.bitIs(bit));
             }
diff --git a/test_regress/t/t_debug_emitv.out b/test_regress/t/t_debug_emitv.out
index abfcc0c61..2fcd6e906 100644
--- a/test_regress/t/t_debug_emitv.out
+++ b/test_regress/t/t_debug_emitv.out
@@ -285,7 +285,7 @@ module Vt_debug_emitv_t;
             if ((PKG_PARAM != 'sh1)) begin
                 $stop;
             end
-            sub.r = 62;
+            sub.r = 62.0;
             $display("%g", $log10(r));
             $display("%g", $ln(r));
             $display("%g", $exp(r));
diff --git a/test_regress/t/t_math_real.v b/test_regress/t/t_math_real.v
index 661837d61..6e0584d5f 100644
--- a/test_regress/t/t_math_real.v
+++ b/test_regress/t/t_math_real.v
@@ -36,6 +36,9 @@ module t (/*AUTOARG*/
    realtime  uninit;
    initial if (uninit != 0.0) $stop;
 
+   localparam int TWENTY = 20;
+   localparam real TWENDIV = $ceil((real'(TWENTY)-14.0)/2.0);
+
    sub_cast_bug374 sub (.cyc5(cyc[4:0]), .*);
 
    initial begin
@@ -163,6 +166,9 @@ module t (/*AUTOARG*/
       r = -$sqrt(-1.0);  // NaN
       s = $sformatf("%g", r);
       `checks(s, "nan");
+
+      if (real'(TWENTY) != 20.0) $stop;
+      if (TWENDIV != 3.0) $stop;
    end
 
    // Test loop