With -Wpedentic, warn about bad `pragma

src/V3ParseImp.cpp

@@ -73,6 +73,15 @@ V3ParseImp::~V3ParseImp() {
 //######################################################################
 // Parser utility methods
 
+void V3ParseImp::pragma(const char* textp) {
+    // Handle `pragma directive
+    if (0 == strncmp(textp, "`pragma", strlen("`pragma"))) textp += strlen("`pragma");
+    while (isspace(*textp)) ++textp;
+    if (!*textp) {
+        if (v3Global.opt.pedantic()) yyerrorf("`pragma is missing a pragma_expression.");
+    }
+}
+
 void V3ParseImp::ppline(const char* textp) {
     // Handle `line directive
     FileLine* prevFl = copyOrSameFileLine();

src/V3ParseImp.h

@@ -142,12 +142,13 @@ public:
     int yylexThis();
     static bool optFuture(const string& flag) { return v3Global.opt.isFuture(flag); }
 
-    void ppline(const char* text);
+    void ppline(const char* textp);
+    void pragma(const char* textp);
     void linenoInc() { fileline()->linenoInc(); }
-    void verilatorCmtLint(const char* text, bool on);
+    void verilatorCmtLint(const char* textp, bool on);
     void verilatorCmtLintSave();
     void verilatorCmtLintRestore();
-    void verilatorCmtBad(const char* text);
+    void verilatorCmtBad(const char* textp);
     void errorPreprocDirective(const char* textp);
     void tag(const char* text);
     void tagNodep(AstNode* nodep) { m_tagNodep = nodep; }

src/verilog.l

@@ -923,7 +923,7 @@ vnum    {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
   "`nosuppress_faults"                  { FL_FWD; FL_BRK; }  // Verilog-XL compatibility
   "`nounconnected_drive"                { FL_FWD; FL_BRK; }  // Verilog-XL compatibility
   "`portcoerce"                         { FL_FWD; FL_BRK; }
-  "`pragma"{ws}+[^\n\r]*                { FL_FWD; FL_BRK; }  // Verilog 2005
+  "`pragma"{ws}*[^\n\r]*                { FL_FWD; PARSEP->pragma(yytext); FL_BRK; }  // Verilog 2005
   "`protect"                            { FL_FWD; FL_BRK; }
   "`remove_gatenames"                   { FL_FWD; FL_BRK; }  // Verilog-XL compatibility
   "`remove_netnames"                    { FL_FWD; FL_BRK; }  // Verilog-XL compatibility

test_regress/t/t_pp_pragma_bad.out

@@ -0,0 +1,4 @@
+%Error: t/t_pp_pragma_bad.v:6: `pragma is missing a pragma_expression.
+`pragma
+^~~~~~~
+%Error: Exiting due to

test_regress/t/t_pp_pragma_bad.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(linter => 1);
+
+lint(
+    verilator_flags2 => ["-Wpedantic"],
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_pp_pragma_bad.v

@@ -0,0 +1,6 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2019 by Wilson Snyder.
+
+`pragma