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https://github.com/verilator/verilator.git
synced 2025-01-24 23:34:45 +00:00
Internals: Rename and cleanup some width() usages. No functional change.
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parent
71cd6f7b90
commit
29e24818a1
@ -394,7 +394,7 @@ private:
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nodep->unlinkFrBack()->deleteTree(); nodep=NULL;
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} else if (nodep->varrefp()) {
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// V3LinkResolve should have cleaned most of these up
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if (nodep->varrefp()->width()>1) nodep->v3error("Unsupported: Non-single bit wide signal pos/negedge sensitivity: "
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if (!nodep->varrefp()->width1()) nodep->v3error("Unsupported: Non-single bit wide signal pos/negedge sensitivity: "
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<<nodep->varrefp()->prettyName());
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m_itemSequent = true;
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nodep->varrefp()->varp()->usedClock(true);
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12
src/V3Ast.h
12
src/V3Ast.h
@ -932,15 +932,17 @@ public:
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bool isAllOnes();
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bool isAllOnesV(); // Verilog width rules apply
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// METHODS
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// METHODS - dump and error
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void v3errorEnd(ostringstream& str) const;
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virtual void dump(ostream& str=cout);
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// METHODS - Tree modifications
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AstNode* addNext(AstNode* newp); // Returns this, adds to end of list
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AstNode* addNextNull(AstNode* newp); // Returns this, adds to end of list, NULL is OK
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void addNextHere(AstNode* newp); // Adds after speced node
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void addPrev(AstNode* newp) { replaceWith(newp); newp->addNext(this); }
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void addHereThisAsNext(AstNode* newp); // Adds at old place of this, this becomes next
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void replaceWith(AstNode* newp); // Replace current node in tree with new node
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void v3errorEnd(ostringstream& str) const;
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virtual void dump(ostream& str=cout);
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AstNode* unlinkFrBack(AstNRelinker* linkerp=NULL); // Unlink this from whoever points to it.
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AstNode* unlinkFrBackWithNext(AstNRelinker* linkerp=NULL); // Unlink this from whoever points to it, keep entire next list with unlinked node
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void swapWith(AstNode* bp);
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@ -1493,7 +1495,7 @@ public:
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inline bool AstNode::isZero() { return (this->castConst() && this->castConst()->num().isEqZero()); }
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inline bool AstNode::isNeqZero() { return (this->castConst() && this->castConst()->num().isNeqZero()); }
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inline bool AstNode::isOne() { return (this->castConst() && this->castConst()->num().isEqOne()); }
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inline bool AstNode::isAllOnes() { return (this->castConst() && this->castConst()->num().isEqAllOnes(this->width())); }
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inline bool AstNode::isAllOnesV() { return (this->castConst() && this->castConst()->num().isEqAllOnes(this->widthMin())); }
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inline bool AstNode::isAllOnes() { return (this->castConst() && this->castConst()->isEqAllOnes()); }
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inline bool AstNode::isAllOnesV() { return (this->castConst() && this->castConst()->isEqAllOnesV()); }
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#endif // Guard
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@ -49,18 +49,18 @@ public:
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AstConst(FileLine* fl, const V3Number& num)
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:AstNodeMath(fl)
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,m_num(num) {
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width(m_num.width(), m_num.sized()?0:m_num.minWidth());
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width(m_num.width(), m_num.sized()?0:m_num.widthMin());
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numeric(m_num.isDouble() ? AstNumeric::DOUBLE
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: m_num.isSigned() ? AstNumeric::SIGNED
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: AstNumeric::UNSIGNED);
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}
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AstConst(FileLine* fl, uint32_t num)
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:AstNodeMath(fl)
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,m_num(V3Number(fl,32,num)) { width(m_num.width(), m_num.sized()?0:m_num.minWidth()); }
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,m_num(V3Number(fl,32,num)) { width(m_num.width(), m_num.sized()?0:m_num.widthMin()); }
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class Unsized32 {}; // for creator type-overload selection
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AstConst(FileLine* fl, Unsized32, uint32_t num) // Unsized 32-bit integer of specified value
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:AstNodeMath(fl)
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,m_num(V3Number(fl,32,num)) { m_num.width(32,false); width(32,m_num.minWidth()); }
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,m_num(V3Number(fl,32,num)) { m_num.width(32,false); width(32,m_num.widthMin()); }
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class RealDouble {}; // for creator type-overload selection
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AstConst(FileLine* fl, RealDouble, double num)
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:AstNodeMath(fl)
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@ -87,6 +87,8 @@ public:
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virtual bool same(AstNode* samep) const {
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return num().isCaseEq(samep->castConst()->num()); }
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virtual int instrCount() const { return widthInstrs(); }
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bool isEqAllOnes() const { return num().isEqAllOnes(width()); }
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bool isEqAllOnesV() const { return num().isEqAllOnes(widthMin()); }
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};
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struct AstConstString : public AstNodeMath {
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@ -2595,8 +2597,8 @@ struct AstRedXor : public AstNodeUniop {
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virtual string emitVerilog() { return "%f(^ %l)"; }
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virtual string emitC() { return "VL_REDXOR_%lq(%lW, %P, %li)"; }
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virtual bool cleanOut() {return false;}
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virtual bool cleanLhs() {return (lhsp()->width()!=1 && lhsp()->width()!=2 && lhsp()->width()!=4
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&& lhsp()->width()!=8 && lhsp()->width()!=16);}
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virtual bool cleanLhs() {int w = lhsp()->width();
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return (w!=1 && w!=2 && w!=4 && w!=8 && w!=16); }
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virtual bool sizeMattersLhs() {return false;}
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virtual int instrCount() const { return 1+V3Number::log2b(width()); }
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};
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@ -24,7 +24,7 @@
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// For each math operator, if it requires a clean operand,
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// and the operand is dirty, insert a CLEAN node.
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// Resize operands to C++ 32/64/wide types.
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// Copy all width() values to minWidth() so RANGE, etc can still see orig widths
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// Copy all width() values to widthMin() so RANGE, etc can still see orig widths
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//
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//*************************************************************************
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@ -47,7 +47,7 @@ private:
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// NODE STATE
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// Entire netlist:
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// AstNode::user() -> CleanState. For this node, 0==UNKNOWN
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// AstNode::user2() -> bool. True indicates minWidth has been propagated
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// AstNode::user2() -> bool. True indicates widthMin has been propagated
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AstUser1InUse m_inuser1;
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AstUser2InUse m_inuser2;
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@ -83,10 +83,9 @@ private:
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AstVarScope* getCreateLastClk(AstVarScope* vscp) {
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if (vscp->user1p()) return ((AstVarScope*)vscp->user1p());
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AstVar* varp = vscp->varp();
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if (varp->width()!=1) varp->v3error("Unsupported: Clock edge on non-single bit signal: "<<varp->prettyName());
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if (!varp->width1()) varp->v3error("Unsupported: Clock edge on non-single bit signal: "<<varp->prettyName());
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string newvarname = ((string)"__Vclklast__"+vscp->scopep()->nameDotless()+"__"+varp->shortName());
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AstVar* newvarp = new AstVar (vscp->fileline(), AstVarType::MODULETEMP, newvarname, AstLogicPacked(), 1);
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newvarp->width(1,1);
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m_modp->addStmtp(newvarp);
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AstVarScope* newvscp = new AstVarScope(vscp->fileline(), m_scopep, newvarp);
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vscp->user1p(newvscp);
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@ -552,7 +552,7 @@ public:
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nodep->v3error("Unsupported: 4-state numbers in this context");
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} else if (nodep->isWide()) {
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putbs("VL_CONST_W_");
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puts(cvtToStr(VL_WORDS_I(nodep->num().minWidth())));
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puts(cvtToStr(VL_WORDS_I(nodep->num().widthMin())));
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puts("X(");
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puts(cvtToStr(nodep->widthMin()));
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puts(",");
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@ -564,7 +564,7 @@ public:
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} else {
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assigntop->iterateAndNext(*this);
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}
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for (int word=VL_WORDS_I(nodep->num().minWidth())-1; word>0; word--) {
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for (int word=VL_WORDS_I(nodep->num().widthMin())-1; word>0; word--) {
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// Only 32 bits - llx + long long here just to appease CPP format warning
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ofp()->printf(",0x%08" VL_PRI64 "x", (vluint64_t)(nodep->num().dataWord(word)));
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}
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@ -149,7 +149,8 @@ private:
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AstNode* decp = new AstAssign(nodep->fileline(), new AstVarRef(nodep->fileline(), varp, true),
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new AstSub(nodep->fileline(), new AstVarRef(nodep->fileline(), varp, false),
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new AstConst(nodep->fileline(), 1)));
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AstNode* zerosp = new AstConst(nodep->fileline(), 0); zerosp->numeric(AstNumeric::SIGNED);
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V3Number zero (nodep->fileline(), 32, 0); zero.isSigned(true);
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AstNode* zerosp = new AstConst(nodep->fileline(), zero);
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AstNode* condp = new AstGtS(nodep->fileline(), new AstVarRef(nodep->fileline(), varp, false),
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zerosp);
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AstNode* bodysp = nodep->bodysp(); if (bodysp) bodysp->unlinkFrBackWithNext();
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@ -626,7 +626,7 @@ bool V3Number::isLt(const V3Number& rhs) const {
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return 0;
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}
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int V3Number::minWidth() const {
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int V3Number::widthMin() const {
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for(int bit=width()-1; bit>0; bit--) {
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if (!bitIs0(bit)) return bit+1;
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}
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@ -150,7 +150,7 @@ public:
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string displayed(const string& format) const;
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static bool displayedFmtLegal(char format); // Is this a valid format letter?
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int width() const { return m_width; }
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int minWidth() const; // Minimum width that can represent this number (~== log2(num)+1)
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int widthMin() const; // Minimum width that can represent this number (~== log2(num)+1)
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bool sized() const { return m_sized; }
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bool autoExtend() const { return m_autoExtend; }
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bool isFromString() const { return m_fromString; }
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@ -85,12 +85,12 @@ enum Stage { PRELIM=1,FINAL=2,BOTH=3 };
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class WidthVP : public AstNUser {
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// Parameters to pass down hierarchy with visit functions.
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int m_width; // Expression width, for (2+2), it's 32 bits
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int m_minWidth; // Minimum width, for (2+2), it's 2 bits, for 32'2+32'2 it's 32 bits
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int m_widthMin; // Minimum width, for (2+2), it's 2 bits, for 32'2+32'2 it's 32 bits
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Stage m_stage; // If true, report errors
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public:
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WidthVP(int width, int minWidth, Stage stage) : m_width(width), m_minWidth(minWidth), m_stage(stage) {}
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WidthVP(int width, int widthMin, Stage stage) : m_width(width), m_widthMin(widthMin), m_stage(stage) {}
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int width() const { return m_width; }
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int widthMin() const { return m_minWidth?m_minWidth:m_width; }
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int widthMin() const { return m_widthMin?m_widthMin:m_width; }
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bool prelim() const { return m_stage&1; }
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bool final() const { return m_stage&2; }
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};
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@ -526,7 +526,7 @@ private:
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if (nodep->num().sized()) {
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nodep->width(nodep->num().width(), nodep->num().width());
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} else {
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nodep->width(nodep->num().width(), nodep->num().minWidth());
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nodep->width(nodep->num().width(), nodep->num().widthMin());
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}
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}
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// We don't size the constant until we commit the widths, as need parameters
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@ -1474,7 +1474,7 @@ private:
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checkCvtUS(nodep->lhsp());
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}
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int width = nodep->lhsp()->width();
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int ewidth = nodep->lhsp()->width(); // Not minWidth; force it.
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int ewidth = nodep->lhsp()->width(); // Not widthMin; force it.
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nodep->width(width,ewidth);
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nodep->numeric(rs_out);
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if (vup->c()->final()) {
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@ -126,7 +126,7 @@ private:
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AstNode* newp = new AstSub(rhsp->fileline(),
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new AstConst(rhsp->fileline(), AstConst::Unsized32(), lhs),
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rhsp);
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newp->numericFrom(rhsp); // Important as AstSub default is lhs's sign
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newp->widthSignedFrom(rhsp); // Important as AstSub default is lhs's sign
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return newp;
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}
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