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Remove out of range Sel in V3Unknown (#5443)

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Fixes #5393
This commit is contained in:
Geza Lore 2024-09-09 14:09:29 +01:00 committed by GitHub
parent 07bb8c701d
commit 2890126110
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4 changed files with 46 additions and 3 deletions
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2
src/V3DfgPeephole.cpp
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@ -750,7 +750,7 @@ class V3DfgPeephole final : public DfgVisitor {
// Full width select, replace with the source.
if (fromp->width() == width) {
UASSERT_OBJ(lsb == 0, fromp, "OOPS");
UASSERT_OBJ(lsb == 0, fromp, "Out of range select should have been fixed up earlier");
APPLYING(REMOVE_FULL_WIDTH_SEL) {
replace(vtxp, fromp);
return;

6
src/V3Unknown.cpp
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@ -410,8 +410,10 @@ class UnknownVisitor final : public VNVisitor {
nodep->unlinkFrBack(&replaceHandle);
V3Number xnum{nodep, nodep->width()};
xnum.setAllBitsX();
AstNode* const newp = new AstCondBound{nodep->fileline(), condp, nodep,
new AstConst{nodep->fileline(), xnum}};
AstNodeExpr* const xexprp = new AstConst{nodep->fileline(), xnum};
AstNodeExpr* const newp
= condp->isZero() ? xexprp
: new AstCondBound{nodep->fileline(), condp, nodep, xexprp};
if (debug() >= 9) newp->dumpTree("- _new: ");
// Link in conditional
replaceHandle.relink(newp);

16
test_regress/t/t_out_of_range_sel.py Executable file
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@ -0,0 +1,16 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.compile(verilator_flags2=["-Wno-SELRANGE"])
test.passes()

25
test_regress/t/t_out_of_range_sel.v Normal file
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@ -0,0 +1,25 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2024 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module serial_adder(
input cin,
output cout
);
localparam WIDTH = 8;
wire [WIDTH:0] c;
generate for (genvar i = 0; i < WIDTH; i++)
full_adder fa(c[i+1]);
endgenerate
assign c[0] = cin;
assign cout = c[WIDTH+1]; // intentional out-of-range
endmodule
module full_adder (output cout);
endmodule