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Define SYSTEMVERILOG, SV_COV_START and other IEEE mandated predefines.

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Wilson Snyder 2013-01-16 19:11:56 -05:00
parent 0437d0abea
commit 2879684f21
6 changed files with 64 additions and 1 deletions
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1
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@ -14,6 +14,7 @@ indicates the contributor was also the author of the fix; Thanks!
*** Fix pin width mismatch error, bug595. [Alex Solomatnikov]
**** Define SYSTEMVERILOG, SV_COV_START and other IEEE mandated predefines.
* Verilator 3.844 2013/01/09

5
bin/verilator
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@ -2070,6 +2070,11 @@ functions, the Verilog signals must be declared with /*verilator public*/.
See also the public task feature; writing an accessor may result in cleaner
code.
=item `SYSTEMVERILOG
The SYSTEMVERILOG, SV_COV_START and related standard defines are set by
default when --language is 1800-*.
=item `VERILATOR
=item `verilator

1
src/V3LangCode.h
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@ -57,6 +57,7 @@ public:
return names[m_e];
};
static V3LangCode mostRecent() { return V3LangCode(L1800_2009); }
bool systemVerilog() const { return m_e == L1800_2005 || m_e == L1800_2009; }
bool legal() const { return m_e != L_ERROR; }
//
enum en m_e;

20
src/V3PreShell.cpp
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@ -70,6 +70,26 @@ protected:
s_preprocp->defineCmdLine(prefl,"verilator3", "1"); // LEAK_OK
s_preprocp->defineCmdLine(prefl,"systemc_clock", "/*verilator systemc_clock*/"); // LEAK_OK
s_preprocp->defineCmdLine(prefl,"coverage_block_off", "/*verilator coverage_block_off*/"); // LEAK_OK
if (prefl->language().systemVerilog()) {
// Synthesis compatibility
s_preprocp->defineCmdLine(prefl,"SYSTEMVERILOG", "1"); // LEAK_OK
// IEEE predefined
s_preprocp->defineCmdLine(prefl,"SV_COV_START", "0");
s_preprocp->defineCmdLine(prefl,"SV_COV_STOP", "1");
s_preprocp->defineCmdLine(prefl,"SV_COV_RESET", "2");
s_preprocp->defineCmdLine(prefl,"SV_COV_CHECK", "3");
s_preprocp->defineCmdLine(prefl,"SV_COV_MODULE", "10");
s_preprocp->defineCmdLine(prefl,"SV_COV_HIER", "11");
s_preprocp->defineCmdLine(prefl,"SV_COV_ASSERTION", "20");
s_preprocp->defineCmdLine(prefl,"SV_COV_FSM_STATE", "21");
s_preprocp->defineCmdLine(prefl,"SV_COV_STATEMENT", "22");
s_preprocp->defineCmdLine(prefl,"SV_COV_TOGGLE", "23");
s_preprocp->defineCmdLine(prefl,"SV_COV_OVERFLOW", "-2");
s_preprocp->defineCmdLine(prefl,"SV_COV_ERROR", "-1");
s_preprocp->defineCmdLine(prefl,"SV_COV_NOCOV", "0");
s_preprocp->defineCmdLine(prefl,"SV_COV_OK", "1");
s_preprocp->defineCmdLine(prefl,"SV_COV_PARTIAL", "2");
}
}
}

20
test_regress/t/t_preproc.out
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@ -790,5 +790,23 @@ module t;
endmodule
predef 0 0
predef 1 1
predef 2 2
predef 3 3
predef 10 10
predef 11 11
predef 20 20
predef 21 21
predef 22 22
predef 23 23
predef -2 -2
predef -1 -1
predef 0 0
predef 1 1
predef 2 2
`line 526 "t/t_preproc.v" 2
`line 544 "t/t_preproc.v" 2

18
test_regress/t/t_preproc.v
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@ -522,3 +522,21 @@ module t;
`undef A `undef STR
endmodule
//======================================================================
// IEEE mandated predefines
`undefineall // undefineall should have no effect on these
predef `SV_COV_START 0
predef `SV_COV_STOP 1
predef `SV_COV_RESET 2
predef `SV_COV_CHECK 3
predef `SV_COV_MODULE 10
predef `SV_COV_HIER 11
predef `SV_COV_ASSERTION 20
predef `SV_COV_FSM_STATE 21
predef `SV_COV_STATEMENT 22
predef `SV_COV_TOGGLE 23
predef `SV_COV_OVERFLOW -2
predef `SV_COV_ERROR -1
predef `SV_COV_NOCOV 0
predef `SV_COV_OK 1
predef `SV_COV_PARTIAL 2
//======================================================================