github/verilator
1
0
Fork 1
mirror of https://github.com/verilator/verilator.git synced 2025-04-05 12:12:39 +00:00
Code Issues Packages Projects Releases Wiki Activity

Tests: Add UVM test that generates ok with known issues commented out. (#1538) (#3267) (#4125) (#4323) (#4349) (#4465) (#4467) (#4468) (#4470) (#4493) (#4494) (#4495) (#4496) (#4497)

Browse Source
This commit is contained in:
Wilson Snyder 2023-09-15 20:26:46 -04:00
parent 07013da13d
commit 26ed2a06a0
5 changed files with 34304 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
test_regress/t/t_dist_copyright.pl
View File

@ -42,6 +42,7 @@ our @Exempt_Files_List = qw(
test_regress/t/t_incr_void.v
test_regress/t/t_timing_trace_fst.pl
test_regress/t/t_uvm_pkg_all.vh
test_regress/t/t_uvm_pkg_todo.vh
test_regress/t/t_wrapper_context.pl
test_regress/t/t_wrapper_context_fst.pl
test_regress/t/t_wrapper_context_seq.pl

5
test_regress/t/t_uvm_all.pl
View File

@ -10,11 +10,12 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
scenarios(vlt => 1);
lint(
compile(
v_flags2 => ["--timing",
"-Wno-PKGNODECL -Wno-UNPACKED -Wno-RANDC -Wno-IMPLICITSTATIC -Wno-CONSTRAINTIGN -Wno-MISINDENT",
"-Wno-PKGNODECL -Wno-RANDC -Wno-IMPLICITSTATIC -Wno-CONSTRAINTIGN -Wno-MISINDENT",
"-Wno-WIDTHEXPAND -Wno-WIDTHTRUNC -Wno-CASTCONST -Wno-REALCVT",
"--error-limit 200 --debug-exit-uvm"],
verilator_make_gmake => 0,
);
#execute(

34254
test_regress/t/t_uvm_pkg_todo.vh Normal file
View File

File diff suppressed because it is too large Load Diff

30
test_regress/t/t_uvm_todo.pl Executable file
View File

@ -0,0 +1,30 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2023 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt => 1);
compile(
v_flags2 => ["--timing",
"-Wno-PKGNODECL -Wno-IMPLICITSTATIC -Wno-CONSTRAINTIGN -Wno-MISINDENT",
"-Wno-CASEINCOMPLETE -Wno-CASTCONST -Wno-SYMRSVDWORD -Wno-WIDTHEXPAND -Wno-WIDTHTRUNC",
"-Wno-REALCVT", # TODO note mostly related to $realtime - could suppress or fix upstream
"-Wno-INFINITELOOP" , # TODO issue #4323, false warning
"-Wno-RANDC", # TODO issue #4349, add support
"-Wno-ZERODLY", # TODO issue #4494, add support
],
verilator_make_gmake => 0,
);
#execute(
# check_finished => 1,
# );
ok(1);
1;

16
test_regress/t/t_uvm_todo.v Normal file
View File

@ -0,0 +1,16 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2023 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`include "t_uvm_pkg_todo.vh"
module t(/*AUTOARG*/);
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule