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Tests: Change default indent to 2 spaces (match edaplayground). No functional change.

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This commit is contained in:
Wilson Snyder 2025-07-03 20:43:13 -04:00
parent f77af4e6f6
commit 26c7f1adb6
11 changed files with 230 additions and 230 deletions
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12
examples/json_py/sub.v
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@ -7,12 +7,12 @@
module sub
#(parameter type TYPE_t = logic)
(
input TYPE_t in,
output TYPE_t out
);
(
input TYPE_t in,
output TYPE_t out
);
// Some simple logic
always_comb out = ~in;
// Some simple logic
always_comb out = ~in;
endmodule

8
examples/make_hello_binary/top.v
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@ -7,8 +7,8 @@
// See also https://verilator.org/guide/latest/examples.html"
module top;
initial begin
$display("Hello World!");
$finish;
end
initial begin
$display("Hello World!");
$finish;
end
endmodule

8
examples/make_hello_c/top.v
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@ -7,8 +7,8 @@
// See also https://verilator.org/guide/latest/examples.html"
module top;
initial begin
$display("Hello World!");
$finish;
end
initial begin
$display("Hello World!");
$finish;
end
endmodule

8
examples/make_hello_sc/top.v
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@ -7,8 +7,8 @@
// See also https://verilator.org/guide/latest/examples.html"
module top;
initial begin
$display("Hello World!");
$finish;
end
initial begin
$display("Hello World!");
$finish;
end
endmodule

40
examples/make_protect_lib/secret_impl.v
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@ -9,29 +9,29 @@
module secret_impl
(
input [31:0] a,
input [31:0] b,
input [31:0] a,
input [31:0] b,
output logic [31:0] x,
input clk,
input reset_l);
input clk,
input reset_l);
logic [31:0] accum_q;
logic [31:0] secret_value;
logic [31:0] accum_q;
logic [31:0] secret_value;
initial $display("[%0t] %m: initialized", $time);
initial $display("[%0t] %m: initialized", $time);
always @(posedge clk) begin
if (!reset_l) begin
accum_q <= 0;
secret_value <= 9;
end
else begin
accum_q <= accum_q + a;
if (accum_q > 10)
x <= b;
else
x <= a + b + secret_value;
end
end
always @(posedge clk) begin
if (!reset_l) begin
accum_q <= 0;
secret_value <= 9;
end
else begin
accum_q <= accum_q + a;
if (accum_q > 10)
x <= b;
else
x <= a + b + secret_value;
end
end
endmodule

64
examples/make_protect_lib/top.v
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@ -8,39 +8,39 @@
module top (input clk);
int cyc;
logic reset_l;
logic [31:0] a;
logic [31:0] b;
logic [31:0] x;
int cyc;
logic reset_l;
logic [31:0] a;
logic [31:0] b;
logic [31:0] x;
verilated_secret secret (.a, .b, .x, .clk, .reset_l);
verilated_secret secret (.a, .b, .x, .clk, .reset_l);
always @(posedge clk) begin
$display("[%0t] cyc=%0d a=%0d b=%0d x=%0d", $time, cyc, a, b, x);
cyc <= cyc + 1;
if (cyc == 0) begin
reset_l <= 0;
a <= 0;
b <= 0;
end
else if (cyc == 1) begin
reset_l <= 1;
a <= 5;
b <= 7;
end
else if (cyc == 2) begin
a <= 6;
b <= 2;
end
else if (cyc == 3) begin
a <= 1;
b <= 9;
end
else if (cyc > 4) begin
$display("Done");
$finish;
end
end
always @(posedge clk) begin
$display("[%0t] cyc=%0d a=%0d b=%0d x=%0d", $time, cyc, a, b, x);
cyc <= cyc + 1;
if (cyc == 0) begin
reset_l <= 0;
a <= 0;
b <= 0;
end
else if (cyc == 1) begin
reset_l <= 1;
a <= 5;
b <= 7;
end
else if (cyc == 2) begin
a <= 6;
b <= 2;
end
else if (cyc == 3) begin
a <= 1;
b <= 9;
end
else if (cyc > 4) begin
$display("Done");
$finish;
end
end
endmodule

48
examples/make_tracing_c/sub.v
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@ -11,32 +11,32 @@ module sub
input reset_l
);
// Example counter/flop
reg [31:0] count_c;
always_ff @(posedge clk) begin
if (!reset_l) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
count_c <= 32'h0;
// End of automatics
// Example counter/flop
reg [31:0] count_c;
always_ff @(posedge clk) begin
if (!reset_l) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
count_c <= 32'h0;
// End of automatics
end
else begin
count_c <= count_c + 1;
if (count_c >= 3) begin
// This write is a magic value the Makefile uses to make sure the
// test completes successfully.
$write("*-* All Finished *-*\n");
$finish;
end
else begin
count_c <= count_c + 1;
if (count_c >= 3) begin
// This write is a magic value the Makefile uses to make sure the
// test completes successfully.
$write("*-* All Finished *-*\n");
$finish;
end
end
end
end
end
// An example assertion
always_ff @(posedge clk) begin
AssertionExample : assert (!reset_l || count_c < 100);
end
// An example assertion
always_ff @(posedge clk) begin
AssertionExample : assert (!reset_l || count_c < 100);
end
// And example coverage analysis
cover property (@(posedge clk) count_c == 3);
// And example coverage analysis
cover property (@(posedge clk) count_c == 3);
endmodule

46
examples/make_tracing_c/top.v
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@ -11,36 +11,36 @@
module top
(
// Declare some signals so we can see how I/O works
input clk,
input reset_l,
input clk,
input reset_l,
output wire [1:0] out_small,
output wire [39:0] out_quad,
output wire [69:0] out_wide,
input [1:0] in_small,
input [39:0] in_quad,
input [69:0] in_wide
input [1:0] in_small,
input [39:0] in_quad,
input [69:0] in_wide
);
// Connect up the outputs, using some trivial logic
assign out_small = ~reset_l ? '0 : (in_small + 2'b1);
assign out_quad = ~reset_l ? '0 : (in_quad + 40'b1);
assign out_wide = ~reset_l ? '0 : (in_wide + 70'b1);
// Connect up the outputs, using some trivial logic
assign out_small = ~reset_l ? '0 : (in_small + 2'b1);
assign out_quad = ~reset_l ? '0 : (in_quad + 40'b1);
assign out_wide = ~reset_l ? '0 : (in_wide + 70'b1);
// And an example sub module. The submodule will print stuff.
sub sub (/*AUTOINST*/
// Inputs
.clk (clk),
.reset_l (reset_l));
// And an example sub module. The submodule will print stuff.
sub sub (/*AUTOINST*/
// Inputs
.clk (clk),
.reset_l (reset_l));
// Print some stuff as an example
initial begin
if ($test$plusargs("trace") != 0) begin
$display("[%0t] Tracing to logs/vlt_dump.vcd...\n", $time);
$dumpfile("logs/vlt_dump.vcd");
$dumpvars();
end
$display("[%0t] Model running...\n", $time);
end
// Print some stuff as an example
initial begin
if ($test$plusargs("trace") != 0) begin
$display("[%0t] Tracing to logs/vlt_dump.vcd...\n", $time);
$dumpfile("logs/vlt_dump.vcd");
$dumpvars();
end
$display("[%0t] Model running...\n", $time);
end
endmodule

76
examples/make_tracing_sc/sub.v
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@ -12,47 +12,47 @@ module sub
input reset_l
);
// Example counter/flop
reg [31:0] count_f;
always_ff @(posedge fastclk) begin
if (!reset_l) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
count_f <= 32'h0;
// End of automatics
end
else begin
count_f <= count_f + 1;
end
end
// Example counter/flop
reg [31:0] count_f;
always_ff @(posedge fastclk) begin
if (!reset_l) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
count_f <= 32'h0;
// End of automatics
end
else begin
count_f <= count_f + 1;
end
end
// Another example flop
reg [31:0] count_c;
always_ff @(posedge clk) begin
if (!reset_l) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
count_c <= 32'h0;
// End of automatics
// Another example flop
reg [31:0] count_c;
always_ff @(posedge clk) begin
if (!reset_l) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
count_c <= 32'h0;
// End of automatics
end
else begin
count_c <= count_c + 1;
if (count_c >= 3) begin
$display("[%0t] fastclk is %0d times faster than clk\n", $time, count_f / count_c);
// This write is a magic value the Makefile uses to make sure the
// test completes successfully.
$write("*-* All Finished *-*\n");
$finish;
end
else begin
count_c <= count_c + 1;
if (count_c >= 3) begin
$display("[%0t] fastclk is %0d times faster than clk\n", $time, count_f / count_c);
// This write is a magic value the Makefile uses to make sure the
// test completes successfully.
$write("*-* All Finished *-*\n");
$finish;
end
end
end
end
end
// An example assertion
always_ff @(posedge clk) begin
AssertionExample : assert (!reset_l || count_c < 100);
end
// An example assertion
always_ff @(posedge clk) begin
AssertionExample : assert (!reset_l || count_c < 100);
end
// And example coverage analysis
cover property (@(posedge clk) count_c == 3);
// And example coverage analysis
cover property (@(posedge clk) count_c == 3);
endmodule

28
examples/make_tracing_sc/top.v
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@ -23,21 +23,21 @@ module top
input [69:0] in_wide
);
// Connect up the outputs, using some trivial logic
assign out_small = ~reset_l ? '0 : (in_small + 2'b1);
assign out_quad = ~reset_l ? '0 : (in_quad + 40'b1);
assign out_wide = ~reset_l ? '0 : (in_wide + 70'b1);
// Connect up the outputs, using some trivial logic
assign out_small = ~reset_l ? '0 : (in_small + 2'b1);
assign out_quad = ~reset_l ? '0 : (in_quad + 40'b1);
assign out_wide = ~reset_l ? '0 : (in_wide + 70'b1);
// And an example sub module. The submodule will print stuff.
sub sub (/*AUTOINST*/
// Inputs
.clk (clk),
.fastclk (fastclk),
.reset_l (reset_l));
// And an example sub module. The submodule will print stuff.
sub sub (/*AUTOINST*/
// Inputs
.clk (clk),
.fastclk (fastclk),
.reset_l (reset_l));
// Print some stuff as an example
initial begin
$display("[%0t] Model running...\n", $time);
end
// Print some stuff as an example
initial begin
$display("[%0t] Model running...\n", $time);
end
endmodule

122
test_regress/t/t_EXAMPLE.v
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@ -21,80 +21,80 @@
`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
// Inputs
clk
);
input clk;
int cyc;
reg [63:0] crc;
reg [63:0] sum;
int cyc;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
Test test(/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
Test test(/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// Test loop
always @(posedge clk) begin
// Test loop
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc == 0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc < 10) begin
sum <= '0;
end
else if (cyc < 90) begin
end
else if (cyc == 99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
`checkh(crc, 64'hc77bb9b3784ea091);
// What checksum will we end up with (above print should match)
`checkh(sum, 64'h4afe43fb79d7b71e);
$write("*-* All Finished *-*\n");
$finish;
end
end
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc == 0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc < 10) begin
sum <= '0;
end
else if (cyc < 90) begin
end
else if (cyc == 99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
`checkh(crc, 64'hc77bb9b3784ea091);
// What checksum will we end up with (above print should match)
`checkh(sum, 64'h4afe43fb79d7b71e);
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test(/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
// Outputs
out,
// Inputs
clk, in
);
// Replace this module with the device under test.
//
// Change the code in the t module to apply values to the inputs and
// merge the output values into the result vector.
// Replace this module with the device under test.
//
// Change the code in the t module to apply values to the inputs and
// merge the output values into the result vector.
input clk;
input [31:0] in;
output reg [31:0] out;
input clk;
input [31:0] in;
output reg [31:0] out;
always @(posedge clk) begin
out <= in;
end
always @(posedge clk) begin
out <= in;
end
endmodule