diff --git a/test_regress/t/t_struct_contents.pl b/test_regress/t/t_struct_contents.pl
new file mode 100755
index 000000000..859050d63
--- /dev/null
+++ b/test_regress/t/t_struct_contents.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2023 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_struct_contents.v b/test_regress/t/t_struct_contents.v
new file mode 100644
index 000000000..d4a244994
--- /dev/null
+++ b/test_regress/t/t_struct_contents.v
@@ -0,0 +1,51 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t(/*AUTOARG*/);
+
+   typedef enum logic [1:0] { ZERO, ONE } enum_t;
+
+   typedef struct packed { bit a; } struct_packed_t;
+   typedef union packed { bit a; } union_packed_t;
+
+   //IEEE 1800-2017 7.2.1
+   // These are all legal
+   typedef struct packed {
+      enum_t e;
+      shortint si;
+      int      it;
+      longint  li;
+      byte     by;
+      bit      bi;
+      logic    lo;
+      reg      rg;
+      integer  in;
+      time     tim;
+      struct_packed_t sp;
+      union_packed_t up;
+      bit [1:0][2:0] bit_array;
+   } legal_t;
+   legal_t legal;
+
+   initial begin
+      legal.e = ONE;
+      legal.si = 1;
+      legal.it = 2;
+      legal.li = 3;
+      legal.by = 4;
+      legal.bi = 1'b1;
+      legal.lo = 1'b1;
+      legal.rg = 1'b1;
+      legal.in = 6;
+      legal.tim = 7;
+      legal.sp.a = 1'b1;
+      legal.up.a = 1'b1;
+      legal.bit_array[1][1] = 1'b1;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule
diff --git a/test_regress/t/t_struct_pat.pl b/test_regress/t/t_struct_pat.pl
new file mode 100755
index 000000000..1aa73f80a
--- /dev/null
+++ b/test_regress/t/t_struct_pat.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_struct_pat.v b/test_regress/t/t_struct_pat.v
new file mode 100644
index 000000000..be82f6556
--- /dev/null
+++ b/test_regress/t/t_struct_pat.v
@@ -0,0 +1,56 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t(/*AUTOARG*/);
+
+   typedef struct {
+      int         a;
+      int         b;
+      byte        c;
+   } sabcu_t;
+
+   typedef struct packed {
+      int         a;
+      int         b;
+      byte        c;
+   } sabcp_t;
+
+   sabcu_t abcu;
+   sabcp_t abcp;
+
+   initial begin
+      abcp = '{1, 2, 3};
+      abcu = '{1, 2, 3};
+      if (abcp.a !== 1) $stop;
+      if (abcp.b !== 2) $stop;
+      if (abcp.c !== 3) $stop;
+      if (abcu.a !== 1) $stop;
+      if (abcu.b !== 2) $stop;
+      if (abcu.c !== 3) $stop;
+
+      abcp = '{default:4, int:5};
+      abcu = '{default:4, int:5};
+      if (abcp.a !== 5) $stop;
+      if (abcp.b !== 5) $stop;
+      if (abcp.c !== 4) $stop;
+      if (abcu.a !== 5) $stop;
+      if (abcu.b !== 5) $stop;
+      if (abcu.c !== 4) $stop;
+
+      abcp = '{int:6, byte:7, int:8};
+      abcu = '{int:6, byte:7, int:8};
+      if (abcp.a !== 8) $stop;
+      if (abcp.b !== 8) $stop;
+      if (abcp.c !== 7) $stop;
+      if (abcu.a !== 8) $stop;
+      if (abcu.b !== 8) $stop;
+      if (abcu.c !== 7) $stop;
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule