From 25b9a16bc75b0191ec02a86367a324ce5e5e5bd6 Mon Sep 17 00:00:00 2001
From: Krzysztof Bieganski <kbieganski@antmicro.com>
Date: Fri, 17 May 2024 13:38:36 +0200
Subject: [PATCH] Fix references to ports in forks (#5123)

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
---
 src/V3Ast.h                   |  2 +-
 src/V3Fork.cpp                |  1 +
 test_regress/t/t_fork_port.pl | 22 ++++++++++++++++++++++
 test_regress/t/t_fork_port.v  | 19 +++++++++++++++++++
 4 files changed, 43 insertions(+), 1 deletion(-)
 create mode 100755 test_regress/t/t_fork_port.pl
 create mode 100644 test_regress/t/t_fork_port.v

diff --git a/src/V3Ast.h b/src/V3Ast.h
index 1392176d3..c910bc4c7 100644
--- a/src/V3Ast.h
+++ b/src/V3Ast.h
@@ -903,7 +903,7 @@ public:
         TRIWIRE,
         TRI0,
         TRI1,
-        PORT,  // Temp type used in parser only
+        PORT,  // Used in parser and V3Fork to recognize ports
         BLOCKTEMP,
         MODULETEMP,
         STMTTEMP,
diff --git a/src/V3Fork.cpp b/src/V3Fork.cpp
index 05b20ec78..d0640c8ea 100644
--- a/src/V3Fork.cpp
+++ b/src/V3Fork.cpp
@@ -616,6 +616,7 @@ class ForkVisitor final : public VNVisitor {
         if (m_forkDepth && !nodep->varp()->isFuncLocal() && nodep->varp()->isClassMember()) return;
 
         if (m_forkDepth && (m_forkLocalsp.count(nodep->varp()) == 0)
+            && nodep->varp()->varType() != VVarType::PORT  // Basically static, so it's safe
             && !nodep->varp()->lifetime().isStatic()) {
             if (nodep->access().isWriteOrRW()
                 && (!nodep->isClassHandleValue() || nodep->user2())) {
diff --git a/test_regress/t/t_fork_port.pl b/test_regress/t/t_fork_port.pl
new file mode 100755
index 000000000..3a7d44569
--- /dev/null
+++ b/test_regress/t/t_fork_port.pl
@@ -0,0 +1,22 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+compile(
+    verilator_flags2 => ["--exe --main --timing"],
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_fork_port.v b/test_regress/t/t_fork_port.v
new file mode 100644
index 000000000..f294278fd
--- /dev/null
+++ b/test_regress/t/t_fork_port.v
@@ -0,0 +1,19 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2024 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+   logic x;
+   sub s(x);
+   initial #1 x = 1;
+endmodule
+
+module sub(input x);
+   initial fork begin
+      @x;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end join_any
+endmodule